2946 lines
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HTML
2946 lines
536 KiB
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Why Is Apple’s M1 Chip So Fast? | Debugger
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Responses (76)
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Andrew Zhu
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about 2 months ago
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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<div role="button" tabindex="0" class="zq zr si zs zt zu ew c">
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<p id="embedded-quote-3fb807533ddc-7fce" class="zv zw gi ka b hh zx hk zy zz aba abb abc abd abe kt gb abf hf" data-selectable-paragraph="">
|
||
<mark class="abg xt ew">PC users may jump ship, but that is a slow process. You don’t leave immediately a platform you are heavily invested in.</mark>
|
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</p>
|
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</div>
|
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<div class="abh s">
|
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<pre class="nb"></pre>
|
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
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Once, Linux and Windows can run on M1 chip. AMD and Intel is doom.
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based on current changing speed, Run Linux and Windows in M1 chip is just a matter of time.
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147
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<button class="ej ek bz ca cb cc cd ce cf bl el em cg en eo"><svg width="29" height="29" class="r q abj" aria-label="responses">
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<path d="M21.27 20.06a9.04 9.04 0 0 0 2.75-6.68C24.02 8.21 19.67 4 14.1 4S4 8.21 4 13.38c0 5.18 4.53 9.39 10.1 9.39 1 0 2-.14 2.95-.41.28.25.6.49.92.7a7.46 7.46 0 0 0 4.19 1.3c.27 0 .5-.13.6-.35a.63.63 0 0 0-.05-.65 8.08 8.08 0 0 1-1.29-2.58 5.42 5.42 0 0 1-.15-.75zm-3.85 1.32l-.08-.28-.4.12a9.72 9.72 0 0 1-2.84.43c-4.96 0-9-3.71-9-8.27 0-4.55 4.04-8.26 9-8.26 4.95 0 8.77 3.71 8.77 8.27 0 2.25-.75 4.35-2.5 5.92l-.24.21v.32a5.59 5.59 0 0 0 .21 1.29c.19.7.49 1.4.89 2.08a6.43 6.43 0 0 1-2.67-1.06c-.34-.22-.88-.48-1.16-.74z"></path></svg><span class="zf abl bv"><span class="ba b sg bc hf">4 replies</span></span></button>
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<button class="ej ek bz ca cb cc cd ce cf bl vu cg en eo">Reply</button>
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<div class="zp s">
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<a href="https://medium.com/@sfx2000?source=responses-----3262b158cba2----1----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
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<h4 class="ba b bb bc hf">
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tim t
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</h4></a>
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</div><a href="https://medium.com/@sfx2000/dont-underestimate-the-value-of-the-toolchain-xcode-is-optimized-for-apple-silicon-and-many-d73c56515c18?source=responses-----3262b158cba2----1----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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</h4></a>
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</div><button class="ew py ij em zo"><svg class="overflow-dots-filled-25px_svg__svgIcon-use" width="25" height="25">
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</div>
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<div class="abh s">
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<pre class="nb"></pre>
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<div class="abi s">
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<h4 class="ba b bb bc hf">
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Don't underestimate the value of the toolchain - xcode is optimized for Apple Silicon (and many years of iOS), and this is tightly coupled the underlying OS - good article, well done
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<span><svg width="25" height="25" viewbox="0 0 25 25" aria-label="clap">
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<path d="M11.74 0l.76 2.97.76-2.97zM14.81 3.78l1.84-2.56-1.42-.47zM8.38 1.22l1.84 2.56L9.8.75zM20.38 21.62a5.11 5.11 0 0 1-3.16 1.61l.49-.45c2.88-2.89 3.45-5.98 1.69-9.21l-1.1-1.94-.96-2.02c-.31-.67-.23-1.18.25-1.55a.84.84 0 0 1 .66-.16c.34.05.66.28.88.6l2.85 5.02c1.18 1.97 1.38 5.12-1.6 8.1M7.1 21.1l-5.02-5.02a1 1 0 0 1 .7-1.7 1 1 0 0 1 .72.3l2.6 2.6a.44.44 0 0 0 .63-.62L4.1 14.04l-1.75-1.75a1 1 0 1 1 1.41-1.41l4.15 4.15a.44.44 0 0 0 .63 0 .44.44 0 0 0 0-.62L4.4 10.26 3.22 9.08a1 1 0 0 1 0-1.4 1.02 1.02 0 0 1 1.41 0l1.18 1.16L9.96 13a.44.44 0 0 0 .62 0 .44.44 0 0 0 0-.63L6.43 8.22a.99.99 0 0 1-.3-.7.99.99 0 0 1 .3-.7 1 1 0 0 1 1.41 0l7 6.98a.44.44 0 0 0 .7-.5l-1.35-2.85c-.31-.68-.23-1.19.25-1.56a.85.85 0 0 1 .66-.16c.34.06.66.28.88.6L18.63 14c1.57 2.88 1.07 5.54-1.55 8.16a5.62 5.62 0 0 1-5.06 1.65 9.35 9.35 0 0 1-4.93-2.72zM11 5.98l2.56 2.56c-.5.6-.56 1.41-.15 2.28l.26.56-4.25-4.25a.98.98 0 0 1-.12-.45 1 1 0 0 1 .29-.7 1.02 1.02 0 0 1 1.41 0zm8.89 2.06c-.38-.56-.9-.92-1.49-1.01a1.74 1.74 0 0 0-1.34.33c-.38.29-.61.65-.71 1.06a2.1 2.1 0 0 0-1.1-.56 1.78 1.78 0 0 0-.99.13l-2.64-2.64a1.88 1.88 0 0 0-2.65 0 1.86 1.86 0 0 0-.48.85 1.89 1.89 0 0 0-2.67-.01 1.87 1.87 0 0 0-.5.9c-.76-.75-2-.75-2.7-.04a1.88 1.88 0 0 0 0 2.66c-.3.12-.61.29-.87.55a1.88 1.88 0 0 0 0 2.66l.62.62a1.88 1.88 0 0 0-.9 3.16l5.01 5.02c1.6 1.6 3.52 2.64 5.4 2.96a7.16 7.16 0 0 0 1.18.1c1.03 0 2-.25 2.9-.7A5.9 5.9 0 0 0 21 22.24c3.34-3.34 3.08-6.93 1.74-9.17l-2.87-5.04z"></path>
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<h4 class="ba b bb bc hf">
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135
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<h4 class="ba b bb bc hf">
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<button class="ej ek bz ca cb cc cd ce cf bl vu cg en eo">Reply</button>
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<img alt="Marc J. Driftmeyer" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/1*wfO-dtsNUUDOiDKN73aQcA.jpeg" width="32" height="32" />
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<a href="https://medium.com/@mdriftmeyer?source=responses-----3262b158cba2----2----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
|
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<h4 class="ba b bb bc hf">
|
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Marc J. Driftmeyer
|
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</h4></a>
|
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</div><a href="https://medium.com/@mdriftmeyer/your-last-paragraph-is-delusional-clap-trap-30774ede1fde?source=responses-----3262b158cba2----2----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
|
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<h4 class="ba b bb bc dv">
|
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about 2 months ago
|
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</h4></a>
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</div>
|
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</div><button class="ew py ij em zo"><svg class="overflow-dots-filled-25px_svg__svgIcon-use" width="25" height="25">
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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</div>
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<div class="abh s">
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<pre class="nb"></pre>
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
|
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Your last paragraph is delusional clap trap. AMD has been developing APUs and was the premier driver of HSA long before Apple got into the game.
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<div class="dm">
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<h4 class="ba b bb bc hf">
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What's worse is you know nothing of Xilinx and how it is going to completely revolutionize AMDs designs…...
|
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</div><button class="abm abn ew"><span class="ba b sg bc abo">Read More</span></button>
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<span><svg width="25" height="25" viewbox="0 0 25 25" aria-label="clap">
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<path d="M11.74 0l.76 2.97.76-2.97zM14.81 3.78l1.84-2.56-1.42-.47zM8.38 1.22l1.84 2.56L9.8.75zM20.38 21.62a5.11 5.11 0 0 1-3.16 1.61l.49-.45c2.88-2.89 3.45-5.98 1.69-9.21l-1.1-1.94-.96-2.02c-.31-.67-.23-1.18.25-1.55a.84.84 0 0 1 .66-.16c.34.05.66.28.88.6l2.85 5.02c1.18 1.97 1.38 5.12-1.6 8.1M7.1 21.1l-5.02-5.02a1 1 0 0 1 .7-1.7 1 1 0 0 1 .72.3l2.6 2.6a.44.44 0 0 0 .63-.62L4.1 14.04l-1.75-1.75a1 1 0 1 1 1.41-1.41l4.15 4.15a.44.44 0 0 0 .63 0 .44.44 0 0 0 0-.62L4.4 10.26 3.22 9.08a1 1 0 0 1 0-1.4 1.02 1.02 0 0 1 1.41 0l1.18 1.16L9.96 13a.44.44 0 0 0 .62 0 .44.44 0 0 0 0-.63L6.43 8.22a.99.99 0 0 1-.3-.7.99.99 0 0 1 .3-.7 1 1 0 0 1 1.41 0l7 6.98a.44.44 0 0 0 .7-.5l-1.35-2.85c-.31-.68-.23-1.19.25-1.56a.85.85 0 0 1 .66-.16c.34.06.66.28.88.6L18.63 14c1.57 2.88 1.07 5.54-1.55 8.16a5.62 5.62 0 0 1-5.06 1.65 9.35 9.35 0 0 1-4.93-2.72zM11 5.98l2.56 2.56c-.5.6-.56 1.41-.15 2.28l.26.56-4.25-4.25a.98.98 0 0 1-.12-.45 1 1 0 0 1 .29-.7 1.02 1.02 0 0 1 1.41 0zm8.89 2.06c-.38-.56-.9-.92-1.49-1.01a1.74 1.74 0 0 0-1.34.33c-.38.29-.61.65-.71 1.06a2.1 2.1 0 0 0-1.1-.56 1.78 1.78 0 0 0-.99.13l-2.64-2.64a1.88 1.88 0 0 0-2.65 0 1.86 1.86 0 0 0-.48.85 1.89 1.89 0 0 0-2.67-.01 1.87 1.87 0 0 0-.5.9c-.76-.75-2-.75-2.7-.04a1.88 1.88 0 0 0 0 2.66c-.3.12-.61.29-.87.55a1.88 1.88 0 0 0 0 2.66l.62.62a1.88 1.88 0 0 0-.9 3.16l5.01 5.02c1.6 1.6 3.52 2.64 5.4 2.96a7.16 7.16 0 0 0 1.18.1c1.03 0 2-.25 2.9-.7A5.9 5.9 0 0 0 21 22.24c3.34-3.34 3.08-6.93 1.74-9.17l-2.87-5.04z"></path>
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the mule
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</div><a href="https://medium.com/@FoolAllTheTime/this-is-absolutely-one-of-the-best-articles-ive-read-in-awhile-39af92a366d9?source=responses-----3262b158cba2----3----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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<pre class="nb"></pre>
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This is absolutely one of the best articles i've read in awhile. Thank you so much, the OoO operation x86 overhang is something new to me. I didn't even realize.
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95
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<path fill-rule="evenodd" clip-rule="evenodd" d="M19.5 1C11.83 1 5.17 5.75 1.9 12.71L1 12.3C4.4 5.02 11.4 0 19.5 0S34.6 5.02 38 12.29l-.9.42C33.82 5.75 27.16 1 19.5 1zM1.9 26.29C5.18 33.25 11.84 38 19.5 38c7.67 0 14.33-4.75 17.6-11.71l.9.42C34.6 33.98 27.6 39 19.5 39S4.4 33.98 1 26.71l.9-.42z"></path></svg>
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</div><img alt="Nicholas Ballard" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/1*QeAQh0DbxpIiDajtj-rVPg.jpeg" width="32" height="32" />
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<a href="https://medium.com/@nball?source=responses-----3262b158cba2----4----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
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<h4 class="ba b bb bc hf">
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Nicholas Ballard
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</h4></a>
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</div><a href="https://medium.com/@nball/this-article-is-good-bec46ff2aae?source=responses-----3262b158cba2----4----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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<pre class="nb"></pre>
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This article is good. Possibly the best article I’ve ever read on Medium. Thorough, technical, opinionated with a well thought out thesis on the new chips. M1 is a step function improvement in SoC. Makes me want to order a new computer though I absolutely don’t need another. :-)
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78
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<path d="M21.27 20.06a9.04 9.04 0 0 0 2.75-6.68C24.02 8.21 19.67 4 14.1 4S4 8.21 4 13.38c0 5.18 4.53 9.39 10.1 9.39 1 0 2-.14 2.95-.41.28.25.6.49.92.7a7.46 7.46 0 0 0 4.19 1.3c.27 0 .5-.13.6-.35a.63.63 0 0 0-.05-.65 8.08 8.08 0 0 1-1.29-2.58 5.42 5.42 0 0 1-.15-.75zm-3.85 1.32l-.08-.28-.4.12a9.72 9.72 0 0 1-2.84.43c-4.96 0-9-3.71-9-8.27 0-4.55 4.04-8.26 9-8.26 4.95 0 8.77 3.71 8.77 8.27 0 2.25-.75 4.35-2.5 5.92l-.24.21v.32a5.59 5.59 0 0 0 .21 1.29c.19.7.49 1.4.89 2.08a6.43 6.43 0 0 1-2.67-1.06c-.34-.22-.88-.48-1.16-.74z"></path></svg><span class="zf abl bv"><span class="ba b sg bc hf">1 reply</span></span></button>
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<button class="ej ek bz ca cb cc cd ce cf bl vu cg en eo">Reply</button>
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<img alt="Charles" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/0*MVCIf-nqLKmSGUtG.jpeg" width="32" height="32" />
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<div class="zp s">
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<a href="https://medium.com/@vigilant?source=responses-----3262b158cba2----5----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
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<h4 class="ba b bb bc hf">
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Charles
|
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</h4></a>
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</div><a href="https://medium.com/@vigilant/just-wanted-to-add-some-thought-from-me-using-the-slowest-m1-laptop-since-last-tuesday-coming-from-dda365c9b0b1?source=responses-----3262b158cba2----5----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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</div><button class="ew py ij em zo"><svg class="overflow-dots-filled-25px_svg__svgIcon-use" width="25" height="25">
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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<pre class="nb"></pre>
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
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Just wanted to add some thought from me using the slowest M1 laptop since last Tuesday, coming from 2019 16 MacBook Pro
|
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</div>
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</div>
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
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The MacBook Air just mercilessly beats the mess out of my 2019 16 MacBook Pro in day to day operations. The MacBook Air will be…...
|
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<img alt="Roberto Brega" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/0*l2lkzBKXDtYWir2p.png" width="32" height="32" />
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Roberto Brega
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</div><a href="https://medium.com/@robi/dear-erik-i-appreciate-your-noble-attempt-at-making-this-topic-accessible-to-the-public-bb1b379f2e1c?source=responses-----3262b158cba2----6----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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<pre class="nb"></pre>
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<h4 class="ba b bb bc hf">
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Dear Erik, I appreciate your noble attempt at making this topic accessible to the public. However, it loses a lot of value if correctness is sacrificed at the altar of simplification.
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Out of the many fallacies in the text, I chose two: A) presenting…...
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63
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<path fill-rule="evenodd" clip-rule="evenodd" d="M19.5 1C11.83 1 5.17 5.75 1.9 12.71L1 12.3C4.4 5.02 11.4 0 19.5 0S34.6 5.02 38 12.29l-.9.42C33.82 5.75 27.16 1 19.5 1zM1.9 26.29C5.18 33.25 11.84 38 19.5 38c7.67 0 14.33-4.75 17.6-11.71l.9.42C34.6 33.98 27.6 39 19.5 39S4.4 33.98 1 26.71l.9-.42z"></path></svg>
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</div><img alt="forrest macgregor" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/2*Da_oEfZeVYZjkWMXBbkFgw.jpeg" width="32" height="32" />
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<h4 class="ba b bb bc hf">
|
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forrest macgregor
|
||
</h4></a>
|
||
</div><a href="https://medium.com/@fauxscot/socs-are-the-bomb-b63b76dd05ca?source=responses-----3262b158cba2----7----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
|
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about 2 months ago
|
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</div><button class="ew py ij em zo"><svg class="overflow-dots-filled-25px_svg__svgIcon-use" width="25" height="25">
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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<pre class="nb"></pre>
|
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
|
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SoC's are the bomb!
|
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</h4>
|
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</div>
|
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</div>
|
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<div class="abi s">
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<div class="dm">
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<h4 class="ba b bb bc hf">
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Physical distance is an issue once propagation delays start approaching processing intervals. There are outfits that make wafer-scale integrated circuits to exploit that one fact. Cray used to base its entire supercomputer line on…...
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73
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<button class="ej ek bz ca cb cc cd ce cf bl vu cg en eo">Reply</button>
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<img alt="Alex Limi" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/1*4K_tL1KgoQAD3eAjp5nSVA.jpeg" width="32" height="32" />
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<a href="https://medium.com/@limi?source=responses-----3262b158cba2----8----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
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<h4 class="ba b bb bc hf">
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Alex Limi
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</h4></a>
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</div><a href="https://medium.com/@limi/specialized-chips-like-this-were-a-cornerstone-of-e-g-ac52dfce3617?source=responses-----3262b158cba2----8----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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<p id="embedded-quote-feb528cab17e-e379" class="zv zw gi ka b hh zx hk zy zz aba abb abc abd abe kt gb abf hf" data-selectable-paragraph="">
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<mark class="abg xt ew">For many years already specialized chips such as the graphical processing units (GPUs) have been sitting in Nvidia and AMD graphics cards performing operations related to graphics much ...</mark>
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<div class="abh s">
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<pre class="nb"></pre>
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Specialized chips like this were a cornerstone of e.g. the Amiga computer (blitter! AGA chipset!), so it predates the AMD/Nvidia graphics chips by many years.
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68
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<img alt="Drew Golden" class="s ii zd ze" src="https://miro.medium.com/fit/c/32/32/0*F61zMwDl_dCqy3eU" width="32" height="32" />
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<a href="https://medium.com/@drew.golden?source=responses-----3262b158cba2----9----------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">
|
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<h4 class="ba b bb bc hf">
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Drew Golden
|
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</h4></a>
|
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</div><a href="https://medium.com/@drew.golden/well-written-piece-thoughtful-and-insighful-nice-work-sir-cf3504382eda?source=responses-----3262b158cba2----9----------------------------" class="ej ek bz ca cb cc cd ce cf bl vu cg en eo" rel="noopener nofollow">
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<h4 class="ba b bb bc dv">
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about 2 months ago
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</div><button class="ew py ij em zo"><svg class="overflow-dots-filled-25px_svg__svgIcon-use" width="25" height="25">
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<path d="M5 12.5c0 .55.2 1.02.59 1.41.39.4.86.59 1.41.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41A1.93 1.93 0 0 0 7 10.5c-.55 0-1.02.2-1.41.59-.4.39-.59.86-.59 1.41zm5.62 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.42.59.55 0 1.02-.2 1.41-.59.4-.39.59-.86.59-1.41 0-.55-.2-1.02-.59-1.41a1.93 1.93 0 0 0-1.41-.59c-.55 0-1.03.2-1.42.59-.39.39-.58.86-.58 1.41zm5.6 0c0 .55.2 1.02.58 1.41.4.4.87.59 1.43.59.56 0 1.03-.2 1.42-.59.39-.39.58-.86.58-1.41 0-.55-.2-1.02-.58-1.41a1.93 1.93 0 0 0-1.42-.59c-.56 0-1.04.2-1.43.59-.39.39-.58.86-.58 1.41z" fill-rule="evenodd"></path></svg></button>
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Well written piece - thoughtful and insighful - nice work sir!
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60
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<span class="jt" id="lo-highlight-meter-1-copy">You have <b>2</b> free member-only stories left this month.</span>
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<span class="jt" id="lo-highlight-meter-1-link"><span><a href="https://medium.com/m/signin?operation=register&redirect=https%3A%2F%2Fdebugger.medium.com%2Fwhy-is-apples-m1-chip-so-fast-3262b158cba2&source=-----3262b158cba2---------------------smart_meter-----------" class="ej ek bz ca cb cc cd ce cf bl cg en eo ll" rel="noopener">Sign up for Medium and get an extra one</a></span></span>
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</section>
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<div>
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<div class="er fb yb fy fz ga"></div>
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<h1 id="8c58" class="gg gh gi gj b gk gl gm gn go gp gq gr gs gt gu gv gw gx gy gz ha hb hc hd he hf">
|
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Why Is Apple’s M1 Chip So Fast?
|
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</h1>
|
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</div>
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<div class="">
|
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<h2 id="d808" class="hg gh gi ba b hh hi hj hk hl hm hn ho hp hq hr hs ht hu hv hw dv">
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Real-world experience with the new M1 Macs has started ticking in. They are fast. Real fast. But why? What is the magic?
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</h2>
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<a href="https://erik-engheim.medium.com/?source=post_page-----3262b158cba2--------------------------------" rel="noopener">
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<path fill-rule="evenodd" clip-rule="evenodd" d="M18 1.87c-6.63 0-12.4 4.14-15.21 10.21L2 11.71C4.94 5.37 11 1 18 1s13.06 4.37 16 10.71l-.79.37C30.4 6.01 24.63 1.88 18 1.88zM2.79 23.92c2.81 6.07 8.58 10.2 15.21 10.2 6.63 0 12.4-4.13 15.21-10.2l.79.37C31.06 30.63 25 35 18 35S4.94 30.63 2 24.29l.79-.37z"></path></svg>
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</div><img alt="Erik Engheim" class="s ii ib ia" src="https://miro.medium.com/fit/c/56/56/0*1Y9ylHZ8csOxgZr7.jpg" width="28" height="28" />
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<h4 class="ba b bb bc fl">
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<span class="ba b bb bc hf">Erik Engheim</span>
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</h4></a></span>
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</div>
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</div><span class="ba b bb bc dv"><a class="" rel="noopener" href="/why-is-apples-m1-chip-so-fast-3262b158cba2?source=post_page-----3262b158cba2--------------------------------">
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<h4 class="ba b bb bc dv">
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<span class="ba b bb bc dv">Nov 28, 2020<span class="in">·</span>23 min read<svg class="ij ik il" width="15" height="15" viewbox="0 0 15 15">
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<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="2880" height="1620" src="https://miro.medium.com/max/2880/1*thz7gKafCYxWoA0h8aGjcg.jpeg" srcset="https://miro.medium.com/max/276/1*thz7gKafCYxWoA0h8aGjcg.jpeg 276w, https://miro.medium.com/max/552/1*thz7gKafCYxWoA0h8aGjcg.jpeg 552w, https://miro.medium.com/max/640/1*thz7gKafCYxWoA0h8aGjcg.jpeg 640w, https://miro.medium.com/max/700/1*thz7gKafCYxWoA0h8aGjcg.jpeg 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/5760/1*thz7gKafCYxWoA0h8aGjcg.jpeg" width="2880" height="1620" srcset="https://miro.medium.com/max/552/1*thz7gKafCYxWoA0h8aGjcg.jpeg 276w, https://miro.medium.com/max/1104/1*thz7gKafCYxWoA0h8aGjcg.jpeg 552w, https://miro.medium.com/max/1280/1*thz7gKafCYxWoA0h8aGjcg.jpeg 640w, https://miro.medium.com/max/1400/1*thz7gKafCYxWoA0h8aGjcg.jpeg 700w" sizes="700px" /></noscript>
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<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
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Image: Apple
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</figcaption>
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</figure>
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<p id="8eb8" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf ku" data-selectable-paragraph="">
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<span class="s kv kw kx eh ky kz la lb lc am">On</span> YouTube, I watched a Mac user who had bought an iMac last year. It was maxed out with 40 GB of RAM costing him about $4,000. He watched in disbelief how his hyperexpensive iMac was being demolished by his new M1 Mac Mini, which he had paid a measly $700 for.
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</p>
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<p id="1408" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
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||
In real-world test after test, the M1 Macs are not merely inching past top-of-the-line Intel Macs, they are destroying them. In disbelief, people have started asking how on earth this is possible?
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</p>
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<p id="71b6" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
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If you are one o<span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm"><span id="rmm">f</span></span></span></span></span></span></span></span></span></span></span></span> those people, you have come to the right place. Here I plan to break it down into digestible pieces exactly what it is that Apple has done with the M1. Specifically the questions I think a lot of people have are:
|
||
</p>
|
||
<ol class="">
|
||
<li id="89bf" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt ld le lf hf" data-selectable-paragraph="">What are the technical reasons this M1 chip is so fast?
|
||
</li>
|
||
<li id="c5cb" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt ld le lf hf" data-selectable-paragraph="">Has Apple made some really exotic technical choices to make this possible?
|
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</li>
|
||
<li id="03e6" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt ld le lf hf" data-selectable-paragraph="">How easy will it be for the competition such as Intel and AMD to pull the same technical tricks?
|
||
</li>
|
||
</ol>
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<p id="6e93" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Sure you could try to Google this, but if you try to learn what Apple has done beyond the superficial explanations, you will quickly get buried in highly technical jargon such as M1 using very wide instruction decoders, enormous reorder buffer (ROB), etc. Unless you are a CPU hardware geek, a lot of this will simply be gobbledygook.
|
||
</p>
|
||
<p id="ecc7" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
To get the most out of this story I advise reading my earlier piece: “<a href="https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de" class="ej ll" target="_blank" rel="noopener">What Does RISC and CISC mean in 2020</a>?” There I explain what a microprocessor (CPU) is as well as various important concepts such as:
|
||
</p>
|
||
<ul class="">
|
||
<li id="4638" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt lm le lf hf" data-selectable-paragraph="">Instruction set architecture (ISA)
|
||
</li>
|
||
<li id="e7aa" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Pipelining
|
||
</li>
|
||
<li id="69ae" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Load/store architecture
|
||
</li>
|
||
<li id="f37f" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Microcode vs. micro-operations
|
||
</li>
|
||
</ul>
|
||
<p id="85a3" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
But if you are impatient, I will do a quick version of the material you need to understand to grasp my explanation of the M1 chip.
|
||
</p>
|
||
<h1 id="a207" class="ln lo gi ba lp lq lr kc ls lt lu kf lv lw lx ly lz ma mb mc md me mf mg mh mi hf" data-selectable-paragraph="">
|
||
What is a microprocessor (CPU)?
|
||
</h1>
|
||
<p id="285c" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
Normally when speaking of chips from Intel and AMD we talk about central processing units (CPUs) or microprocessors. As you can read more about in my <a href="https://medium.com/swlh/what-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de" class="ej ll" target="_blank" rel="noopener">RISC vs. CISC story</a>, these pull in instructions from memory. Then each instruction is typically carried out in sequence.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="n p ak">
|
||
<img alt="A very basic RISC CPU, not the M1" class="mt" src="https://miro.medium.com/proxy/1*3G7uz4l1GnFacxz6InrLLw.png" />
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
A very basic RISC CPU, not the M1. Instructions are moved from memory along <strong class="ba lp">blue</strong> arrows into the instruction register. There a decoder figures out what the instruction is and enables different parts of the CPU through the <strong class="ba lp">red</strong> control lines. The ALU adds and subtracts numbers placed in the registers.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="5525" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
A CPU at its most basic level is a device with a number of named memory cells called registers and a number of computational units called arithmetic logic units (ALU). The ALUs perform things like addition, subtraction, and other basic math operations. However, these are only connected to the CPU registers. If you want to add up two numbers, you have to get those two numbers from memory and into two registers in the CPU.
|
||
</p>
|
||
<p id="db6e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Here are some examples of typical instructions that a RISC CPU as found on the M1 carries out.
|
||
</p>
|
||
<pre class="mo mp mq mr ms mu mv mw"><span id="9500" class="hf mx lo gi my b dl mz na s nb" data-selectable-paragraph="">load r1, 150<br />load r2, 200<br />add r1, r2<br />store r1, 310</span></pre>
|
||
<p id="d5bb" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Here <code class="jo nc nd ne my b">r1</code> and <code class="jo nc nd ne my b">r2</code> are the registers I talked about. Modern RISC CPUs cannot do operations on numbers that are not in a register like this. For example, it cannot add two numbers residing in RAM in two different locations. Instead, it has to pull these two numbers into a separate register. That is what we do in this simple example. We pull in the number at memory location 150 in the RAM and put it into register <code class="jo nc nd ne my b">r1</code> in the CPU. Next, we put the contents of address 200 into register <code class="jo nc nd ne my b">r2</code>. Only then can the numbers be added with the <code class="jo nc nd ne my b">add r1, r2</code> instruction.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nf">
|
||
<div class="jn s am jo">
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||
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||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="400" height="223" src="https://miro.medium.com/max/400/1*kDqSqtumOzNFZdpixUW0IQ.jpeg" srcset="https://miro.medium.com/max/276/1*kDqSqtumOzNFZdpixUW0IQ.jpeg 276w, https://miro.medium.com/max/400/1*kDqSqtumOzNFZdpixUW0IQ.jpeg 400w" sizes="400px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/800/1*kDqSqtumOzNFZdpixUW0IQ.jpeg" width="400" height="223" srcset="https://miro.medium.com/max/552/1*kDqSqtumOzNFZdpixUW0IQ.jpeg 276w, https://miro.medium.com/max/800/1*kDqSqtumOzNFZdpixUW0IQ.jpeg 400w" sizes="400px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
An old mechanical calculator with two registers: the accumulator and input register. Modern CPUs typically have more than a dozen registers, and they are electronic rather than mechanical.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="7146" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The concept of registers is old. For example, on this old mechanical calculator, the <em class="nh">register</em> is what holds the numbers you are adding. Likely the origin of the term <em class="nh">cash register</em>. The register is where you registered input numbers.
|
||
</p>
|
||
<h1 id="22f2" class="ln lo gi ba lp lq lr kc ls lt lu kf lv lw lx ly lz ma mb mc md me mf mg mh mi hf" data-selectable-paragraph="">
|
||
The M1 is not a CPU!
|
||
</h1>
|
||
<p id="d450" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
But here is a very important thing to understand about the M1:
|
||
</p>
|
||
<p id="777f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The M1 is not a CPU, it is a whole system of multiple chips put into one large silicon package. The CPU is just one of these chips.
|
||
</p>
|
||
<p id="69f0" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Basically, the M1 is one whole computer onto a chip. The M1 contains a CPU, graphical processing unit (GPU), memory, input and output controllers, and many more things making up a whole computer. This is what we call a system on a chip (SoC).
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div role="button" tabindex="0" class="je jf am jg v jh">
|
||
<div class="fu fv ni">
|
||
<div class="jn s am jo">
|
||
<div class="nj jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="1200" height="360" src="https://miro.medium.com/max/1200/1*c4EYUAVj4k7n6wWLoWUVdA.png" srcset="https://miro.medium.com/max/276/1*c4EYUAVj4k7n6wWLoWUVdA.png 276w, https://miro.medium.com/max/552/1*c4EYUAVj4k7n6wWLoWUVdA.png 552w, https://miro.medium.com/max/640/1*c4EYUAVj4k7n6wWLoWUVdA.png 640w, https://miro.medium.com/max/700/1*c4EYUAVj4k7n6wWLoWUVdA.png 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/2400/1*c4EYUAVj4k7n6wWLoWUVdA.png" width="1200" height="360" srcset="https://miro.medium.com/max/552/1*c4EYUAVj4k7n6wWLoWUVdA.png 276w, https://miro.medium.com/max/1104/1*c4EYUAVj4k7n6wWLoWUVdA.png 552w, https://miro.medium.com/max/1280/1*c4EYUAVj4k7n6wWLoWUVdA.png 640w, https://miro.medium.com/max/1400/1*c4EYUAVj4k7n6wWLoWUVdA.png 700w" sizes="700px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
M1 is a system on a chip. Meaning all the parts making up a computer are placed on one silicon chip.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="fce1" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Today if you buy a chip — whether from Intel or AMD — you actually get what amounts to <em class="nh">multiple</em> microprocessors in one package. In the past computers would have multiple physically separate chips on the motherboard of the computer.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nk">
|
||
<div class="jn s am jo">
|
||
<div class="nl jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="600" height="418" src="https://miro.medium.com/max/600/1*GBrG4D2YCEVYREXAHIiJnQ.png" srcset="https://miro.medium.com/max/276/1*GBrG4D2YCEVYREXAHIiJnQ.png 276w, https://miro.medium.com/max/552/1*GBrG4D2YCEVYREXAHIiJnQ.png 552w, https://miro.medium.com/max/600/1*GBrG4D2YCEVYREXAHIiJnQ.png 600w" sizes="600px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1200/1*GBrG4D2YCEVYREXAHIiJnQ.png" width="600" height="418" srcset="https://miro.medium.com/max/552/1*GBrG4D2YCEVYREXAHIiJnQ.png 276w, https://miro.medium.com/max/1104/1*GBrG4D2YCEVYREXAHIiJnQ.png 552w, https://miro.medium.com/max/1200/1*GBrG4D2YCEVYREXAHIiJnQ.png 600w" sizes="600px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
Example of a computer motherboard. Memory, CPU, graphics cards, IO controllers, network cards, and many other components can be attached to the motherboard to communicate with each other.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="9cf5" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However because we are able to put so many transistors on a silicon die today, companies such as Intel and AMD began putting multiple microprocessors onto one chip. Today we refer to these chips as CPU cores. One core is basically a full independent chip that can read instructions from memory and perform calculations.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nm">
|
||
<div class="jn s am jo">
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<div class="nn jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="425" height="267" src="https://miro.medium.com/max/425/1*XZsBJV_v4WybnUFYjJJiPQ.gif" srcset="https://miro.medium.com/max/276/1*XZsBJV_v4WybnUFYjJJiPQ.gif 276w, https://miro.medium.com/max/425/1*XZsBJV_v4WybnUFYjJJiPQ.gif 425w" sizes="425px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/850/1*XZsBJV_v4WybnUFYjJJiPQ.gif" width="425" height="267" srcset="https://miro.medium.com/max/552/1*XZsBJV_v4WybnUFYjJJiPQ.gif 276w, https://miro.medium.com/max/850/1*XZsBJV_v4WybnUFYjJJiPQ.gif 425w" sizes="425px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
A microchip with multiple CPU cores.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="18a4" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
This has for a long time been the name of the game in terms of increasing performance: Just add more general-purpose CPU cores. But there is a disturbance in the force. There is one player in the CPU market which is deviating from this trend.
|
||
</p>
|
||
<h2 id="cff4" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
Apple’s not so secret heterogeneous computing strategy
|
||
</h2>
|
||
<p id="8feb" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
Instead of adding ever more general-purpose CPU cores, Apple has followed another strategy: They have started adding ever more specialized chips doing a few specialized tasks. The benefit of this is that specialized chips tend to be able to perform their tasks significantly faster using much less electric current than a general-purpose CPU core.
|
||
</p>
|
||
<p id="e379" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
This is not entirely new knowledge. For many years already specialized chips such as the graphical processing units (GPUs) have been sitting in Nvidia and AMD graphics cards performing operations related to graphics much faster than general-purpose CPUs.
|
||
</p>
|
||
<p id="866e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
What Apple has done is simply to take a more radical shift toward this direction. Rather than just having general-purpose cores and memory, the M1 contains a wide variety of specialized chips:
|
||
</p>
|
||
<ul class="">
|
||
<li id="6e0e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt lm le lf hf" data-selectable-paragraph="">Central processing unit (CPU) — the “brains” of the SoC. Runs most of the code of the operating system and your apps.
|
||
</li>
|
||
<li id="037c" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Graphics processing unit (GPU) — handles graphics-related tasks, such as visualizing an app’s user interface and 2D/3D gaming.
|
||
</li>
|
||
<li id="9a44" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Image processing unit (ISP) — can be used to speed up common tasks done by image processing applications.
|
||
</li>
|
||
<li id="c654" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Digital signal processor (DSP) — handles more mathematically intensive functions than a CPU. Includes decompressing music files.
|
||
</li>
|
||
<li id="1cac" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Neural processing unit (NPU) — used in high-end smartphones to accelerate machine learning (A.I.) tasks. These include voice recognition and camera processing.
|
||
</li>
|
||
<li id="ce8d" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Video encoder/decoder — handles the power-efficient conversion of video files and formats.
|
||
</li>
|
||
<li id="d9a8" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Secure Enclave — encryption, authentication, and security.
|
||
</li>
|
||
<li id="2d2b" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Unified memory — allows the CPU, GPU, and other cores to quickly exchange information.
|
||
</li>
|
||
</ul>
|
||
<p id="967a" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
This is part of the reason why a lot of people working on images and video editing with the M1 Macs are seeing such speed improvements. A lot of the tasks they do can run directly on specialized hardware. That is what allows a cheap M1 Mac Mini to encode a large video file without breaking a sweat while an expensive iMac has all its fans going full blast and still cannot keep up.
|
||
</p>
|
||
<p id="39d6" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Read more about heterogeneous computing: <a href="https://erik-engheim.medium.com/apple-m1-foreshadows-risc-v-dd63a62b2562" class="ej ll" target="_blank" rel="noopener">Apple M1 foreshadows Rise of RISC-V</a>.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nw">
|
||
<div class="jn s am jo">
|
||
<div class="jp jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="576" height="324" src="https://miro.medium.com/max/576/1*SpFJ9g-taH9a-TvXdnaq2w.png" srcset="https://miro.medium.com/max/276/1*SpFJ9g-taH9a-TvXdnaq2w.png 276w, https://miro.medium.com/max/552/1*SpFJ9g-taH9a-TvXdnaq2w.png 552w, https://miro.medium.com/max/576/1*SpFJ9g-taH9a-TvXdnaq2w.png 576w" sizes="576px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1152/1*SpFJ9g-taH9a-TvXdnaq2w.png" width="576" height="324" srcset="https://miro.medium.com/max/552/1*SpFJ9g-taH9a-TvXdnaq2w.png 276w, https://miro.medium.com/max/1104/1*SpFJ9g-taH9a-TvXdnaq2w.png 552w, https://miro.medium.com/max/1152/1*SpFJ9g-taH9a-TvXdnaq2w.png 576w" sizes="576px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
In <strong class="ba lp">blue</strong> you see multiple CPU cores accessing memory, and in <strong class="ba lp">green</strong> you see large numbers of GPU cores accessing memory.
|
||
</figcaption>
|
||
</figure>
|
||
<h2 id="d906" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
What is Special About Apple’s Unified Memory Architecture?
|
||
</h2>
|
||
<p id="956a" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
Apple’s “Unified Memory Architecture” (UMA) is a bit tricky to wrap your head around (I got it wrong first time I wrote it down here).
|
||
</p>
|
||
<p id="8cb3" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
To explain why, we need to take a few steps back.
|
||
</p>
|
||
<p id="b7a7" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For a long time cheap computer systems have had the CPU and GPU integrated into the same chip (same silicon die). These have been famously slow. In the past saying “integrated graphics” was essentially the same as saying “slow graphics.”
|
||
</p>
|
||
<p id="a598" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
These where slow for severals reasons:
|
||
</p>
|
||
<p id="1d41" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Separate areas of this memory got reserved for the CPU and GPU. If the CPU had a chunk of data it wanted the GPU to use, it couldn’t say “here have some of my memory.” No, the CPU had to explicitly copy the whole chunk of data over the memory area controlled by the GPU.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nx">
|
||
<div class="jn s am jo">
|
||
<div class="ny jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="640" height="321" src="https://miro.medium.com/max/640/1*7c67HhuDWVFM3Pi-mO5boA.jpeg" srcset="https://miro.medium.com/max/276/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 276w, https://miro.medium.com/max/552/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 552w, https://miro.medium.com/max/640/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 640w" sizes="640px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1280/1*7c67HhuDWVFM3Pi-mO5boA.jpeg" width="640" height="321" srcset="https://miro.medium.com/max/552/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 276w, https://miro.medium.com/max/1104/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 552w, https://miro.medium.com/max/1280/1*7c67HhuDWVFM3Pi-mO5boA.jpeg 640w" sizes="640px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
CPUs don’t need a lot of data served, but they want it <strong class="ba lp">fast</strong>.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="f669" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
CPUs and GPUs don’t want their memory served the same way. Let us do a silly food analogy: CPUs want their plate of data served very quickly by the waiter, but they are totally cool with small portion sizes. Imagine a fancy French restaurant with waiters on rollerblades to serve you really quickly.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nz">
|
||
<div class="jn s am jo">
|
||
<div class="oa jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="550" height="366" src="https://miro.medium.com/max/550/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg" srcset="https://miro.medium.com/max/276/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg 276w, https://miro.medium.com/max/550/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg 550w" sizes="550px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1100/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg" width="550" height="366" srcset="https://miro.medium.com/max/552/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg 276w, https://miro.medium.com/max/1100/1*ethYaJsPETw2zxF7Xm0Z0w.jpeg 550w" sizes="550px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
This is how your GPU wants their memory: <strong class="ba lp">huge</strong> portions. The more the merrier.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="9c14" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
GPUs in contrast are cool with the waiter being slow to serve the data. But the GPUs want enormous servings. They gobble massive amounts of data because they are massive parallel machines, that can chew through lots of data in parallel. Imagine an American junk food place, where the food takes some time to arrive because they are pushing a whole trolley of food to your seating area.
|
||
</p>
|
||
<p id="812f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
With such different needs, putting CPUs and GPUs on the same physical chip was not a great idea. The GPUs would sit there starving while given small French servings. The result was that there was no point in putting powerful GPUs on an SoC. The tiny portions of data served up, could easily be chewed up by a weak little GPU.
|
||
</p>
|
||
<p id="d539" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The second problem was that large GPUs produce a lot of heat and thus you cannot integrate them with the CPU without getting problems ridding yourself of the heat produced. Thus discrete graphics cards tend to look like the one below: Large beasts with massive cooling fans. They have special dedicated memory designed to serve the greedy cards massive amounts of data.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv ob">
|
||
<div class="jn s am jo">
|
||
<div class="oc jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="389" height="209" src="https://miro.medium.com/max/389/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg" srcset="https://miro.medium.com/max/276/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg 276w, https://miro.medium.com/max/389/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg 389w" sizes="389px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/778/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg" width="389" height="209" srcset="https://miro.medium.com/max/552/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg 276w, https://miro.medium.com/max/778/1*gQcbAlaUXNtjJi6OAUzMsg.jpeg 389w" sizes="389px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
GeForce RTX 3080
|
||
</figcaption>
|
||
</figure>
|
||
<p id="14fa" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
That is why these cards have high performance. But they have an achilles heel: Whenever they have to get data from the memory used by the CPU, this happens over a set of copper traces on the computer motherboard called a PCIe bus. Try chugging water through a super thin straw. It may get to your mouth fast, but the throughput is totally inadequate.
|
||
</p>
|
||
<p id="5fca" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Apple’s <em class="nh">Unified Memory Architecture</em> tries to solve all these problems without having the disadvantages of old school shared memory. They achieve this in the following ways:
|
||
</p>
|
||
<ol class="">
|
||
<li id="dade" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt ld le lf hf" data-selectable-paragraph="">There is no special area reserved just for the CPU or just the GPU. Memory is allocated to both processors. They can both use the same memory. No copying is needed.
|
||
</li>
|
||
<li id="4c61" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt ld le lf hf" data-selectable-paragraph="">Apple uses memory which serves both large chunks of data and serves it fast. In computer speak that is called low latency and high throughput. Thus the need to be connected to separate types of memory is removed.
|
||
</li>
|
||
<li id="2508" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt ld le lf hf" data-selectable-paragraph="">Apple has gotten the watt usage of the GPU down, so that a relatively powerful GPU can be integrated without overheating the SoC. And ARM chips produce less heat, allowing the GPU to have a higher heat budget than a GPU on the same silicon die as an AMD or Intel CPU.
|
||
</li>
|
||
</ol>
|
||
<p id="ba08" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Some will say unified memory is not entirely new. It is true that different systems have had it in the past. But then the difference in memory requirements may not have been as large. Secondly what Nvidia calls Unified Memory is not really the same thing. In the Nvidea world Unified Memory simply means that there is software and hardware which takes care of automatically copying data back and forth between the separate CPU and GPU memory. Thus from a programmers perspective Apple and Nvidia Unified Memory may look the same, but it is not the same in a physical sense.
|
||
</p>
|
||
<p id="2fcb" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
There is of course a tradeoff in this strategy. Getting this high bandwidth memory (big servings) require full integration which means you take away the opportunity from customers to upgrade their memory. But Apple seeks to minimize this problem by making the communication with the SSD disks so fast, that they essentially work like old fashion memory.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div role="button" tabindex="0" class="je jf am jg v jh">
|
||
<div class="fu fv od">
|
||
<div class="jn s am jo">
|
||
<div class="oe jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="834" height="472" src="https://miro.medium.com/max/834/1*IJFHpc1CrblUt09PSzaTyg.png" srcset="https://miro.medium.com/max/276/1*IJFHpc1CrblUt09PSzaTyg.png 276w, https://miro.medium.com/max/552/1*IJFHpc1CrblUt09PSzaTyg.png 552w, https://miro.medium.com/max/640/1*IJFHpc1CrblUt09PSzaTyg.png 640w, https://miro.medium.com/max/700/1*IJFHpc1CrblUt09PSzaTyg.png 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1668/1*IJFHpc1CrblUt09PSzaTyg.png" width="834" height="472" srcset="https://miro.medium.com/max/552/1*IJFHpc1CrblUt09PSzaTyg.png 276w, https://miro.medium.com/max/1104/1*IJFHpc1CrblUt09PSzaTyg.png 552w, https://miro.medium.com/max/1280/1*IJFHpc1CrblUt09PSzaTyg.png 640w, https://miro.medium.com/max/1400/1*IJFHpc1CrblUt09PSzaTyg.png 700w" sizes="700px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
How Mac’s used GPUs before unified memory. There was even an option of having graphics cards outside the computer using a Thunderbolt 3 cable. There is some speculation that this may still be possible in the future.
|
||
</figcaption>
|
||
</figure>
|
||
<h2 id="d329" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
If SoCs Are So Smart, Why Don’t Intel and AMD Copy This Strategy?
|
||
</h2>
|
||
<p id="f5e0" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
If what Apple is doing is so smart, why is not everybody doing it? To some extent they are. Other ARM chip makers are increasingly putting in specialized hardware.
|
||
</p>
|
||
<p id="2bdd" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
AMD has also started putting stronger GPUs on some of their chips and moving gradually toward some form of SoC with the accelerated processing units (APU) which are basically CPU cores and GPU cores placed on the same silicon die.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div role="button" tabindex="0" class="je jf am jg v jh">
|
||
<div class="fu fv of">
|
||
<div class="jn s am jo">
|
||
<div class="og jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="900" height="540" src="https://miro.medium.com/max/900/1*vutPH0zsrwSzGgFWomL61A.jpeg" srcset="https://miro.medium.com/max/276/1*vutPH0zsrwSzGgFWomL61A.jpeg 276w, https://miro.medium.com/max/552/1*vutPH0zsrwSzGgFWomL61A.jpeg 552w, https://miro.medium.com/max/640/1*vutPH0zsrwSzGgFWomL61A.jpeg 640w, https://miro.medium.com/max/700/1*vutPH0zsrwSzGgFWomL61A.jpeg 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1800/1*vutPH0zsrwSzGgFWomL61A.jpeg" width="900" height="540" srcset="https://miro.medium.com/max/552/1*vutPH0zsrwSzGgFWomL61A.jpeg 276w, https://miro.medium.com/max/1104/1*vutPH0zsrwSzGgFWomL61A.jpeg 552w, https://miro.medium.com/max/1280/1*vutPH0zsrwSzGgFWomL61A.jpeg 640w, https://miro.medium.com/max/1400/1*vutPH0zsrwSzGgFWomL61A.jpeg 700w" sizes="700px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
AMD Ryzen Accelerated Processing Unit (APU) which combines CPU and GPU (Radeon Vega) on one silicon chip. Does however not contain other co-processors, IO-controllers, or unified memory.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="279e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Yet there are important reasons why they cannot do this. An SoC is essentially a whole computer on a chip. That makes it a more natural fit for an actual computer-maker, such as HP and Dell. Let me clarify with a silly car analogy: If your business model is to build and sell car engines, it would be an unusual leap to begin manufacturing and selling whole cars.
|
||
</p>
|
||
<p id="04e1" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For ARM, in contrast, this isn’t an issue. Computer makers such as Dell or HP could simply license ARM intellectual property and buy IP for other chips, to add whatever specialized hardware they think their SoC should have. Next, they ship the finished design over to a semiconductor foundry such as <a href="https://en.wikipedia.org/wiki/GlobalFoundries" class="ej ll" target="_blank" rel="noopener nofollow">GlobalFoundries</a> or <a href="https://www.tsmc.com/english" class="ej ll" target="_blank" rel="noopener nofollow">TSMC</a>, which manufactures chips for AMD and Apple today.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div role="button" tabindex="0" class="je jf am jg v jh">
|
||
<div class="fu fv oh">
|
||
<div class="jn s am jo">
|
||
<div class="oi jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="748" height="460" src="https://miro.medium.com/max/748/1*d88lw8YMonKgdDWQLC1jXQ.jpeg" srcset="https://miro.medium.com/max/276/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 276w, https://miro.medium.com/max/552/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 552w, https://miro.medium.com/max/640/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 640w, https://miro.medium.com/max/700/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1496/1*d88lw8YMonKgdDWQLC1jXQ.jpeg" width="748" height="460" srcset="https://miro.medium.com/max/552/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 276w, https://miro.medium.com/max/1104/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 552w, https://miro.medium.com/max/1280/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 640w, https://miro.medium.com/max/1400/1*d88lw8YMonKgdDWQLC1jXQ.jpeg 700w" sizes="700px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
TSMC semiconductor foundry in Taiwan. TSMC manufactures chips for other companies such as AMD, Apple, Nvidia, and Qualcomm.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="a601" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Here we get a big problem with the Intel and AMD business model. Their business models are based on selling general-purpose CPUs, which people just slot onto a large PC motherboard. Thus computer-makers can simply buy motherboards, memory, CPUs, and graphics cards from different vendors and integrate them into one solution.
|
||
</p>
|
||
<p id="7f77" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
But we are quickly moving away from that world. In the new SoC world, you don’t assemble physical components from different vendors. Instead, you assemble IP (intellectual property) from different vendors. You buy the design for graphics cards, CPUs, modems, IO controllers, and other things from different vendors and use that to design an SoC in-house. Then you get a foundry to manufacture this.
|
||
</p>
|
||
<p id="2fba" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Now you got a big problem, because neither Intel, AMD, or Nvidia are going to license their intellectual property to Dell or HP for them to make an SoC for their machines.
|
||
</p>
|
||
<p id="b24c" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC-makers may have different ideas of what they should contain. You potentially get a conflict between Intel, AMD, Microsoft, and PC-makers about what sort of specialized chips should be included because these will need software support.
|
||
</p>
|
||
<p id="558d" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For Apple this is simple. They control the whole widget. They give you, for example, the Core ML library for developers to write <a href="https://developer.apple.com/machine-learning/" class="ej ll" target="_blank" rel="noopener nofollow">machine learning</a> stuff. Whether Core ML runs on Apple’s CPU or the Neural Engine is an implementation detail developers don’t have to care about.
|
||
</p>
|
||
<h2 id="711f" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
The fundamental challenge of making any CPU run fast
|
||
</h2>
|
||
<p id="f11c" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
So heterogeneous computing is part of the reason but not the sole reason. The fast general-purpose CPU cores on the M1, called Firestorm, are genuinely fast. This is a major deviation from ARM CPU cores in the past which tended to be very weak compared to AMD and Intel cores.
|
||
</p>
|
||
<p id="b74c" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Firestorm, in contrast, beats most Intel cores and almost beats the fastest AMD Ryzen cores. Conventional wisdom said that was not going to happen.
|
||
</p>
|
||
<p id="ab49" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Before talking about what makes Firestorm fast it helps to understand what the core idea of making a fast CPU is really about.
|
||
</p>
|
||
<p id="92fc" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
In principle you accomplish in a combination of two strategies:
|
||
</p>
|
||
<ol class="">
|
||
<li id="68be" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt ld le lf hf" data-selectable-paragraph="">Perform more instructions in a sequence faster.
|
||
</li>
|
||
<li id="5f98" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt ld le lf hf" data-selectable-paragraph="">Perform lots of instructions in parallel.
|
||
</li>
|
||
</ol>
|
||
<p id="bd92" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Back in the ’80s, it was easy. Just increase the clock frequency and the instructions would finish faster. Every clock cycle is when the computer does something. But this <em class="nh">something</em> can be quite little. Thus an instruction may require multiple clock cycles to finish because it is made up of several smaller tasks.
|
||
</p>
|
||
<p id="905f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However, today increasing the clock frequency is next to impossible. That is the whole “End of Moore’s Law” that people have been harping on for over a decade now.
|
||
</p>
|
||
<p id="2133" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Thus it is really about executing as many instructions as possible in parallel.
|
||
</p>
|
||
<h2 id="1f1b" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
Multi-core or Out-of-Order processors?
|
||
</h2>
|
||
<p id="9966" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
There are two approaches to this.
|
||
</p>
|
||
<ul class="">
|
||
<li id="23a9" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt lm le lf hf" data-selectable-paragraph="">Add more CPU cores. Each core works independent and in parallel.
|
||
</li>
|
||
<li id="1299" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Make each CPU core execute multiple instructions in parallel.
|
||
</li>
|
||
</ul>
|
||
<p id="6553" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For a software developer, adding cores is like adding <em class="nh">threads</em>. Every CPU core is like a hardware thread.
|
||
</p>
|
||
<p id="5a7a" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
If you don’t know what a thread is, then you can think of it as the process of carrying out a task. With two cores, a CPU can carry out two separate tasks concurrently: two threads. The tasks could be described as two separate programs stores in memory or it could actually be the same program performed twice. Each thread needs some bookkeeping, such as <em class="nh">where</em> in a sequence of program instructions the thread is currently at. Each thread may store temporary results which should be kept separate.
|
||
</p>
|
||
<p id="8059" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
In principle, a processor can have just one core and run multiple threads. In this case, it simply halts one thread and stores current progress before switching to another. Later it switches back. This doesn’t bring much of a performance enhancement unless the thread has to frequently halt to:
|
||
</p>
|
||
<ul class="">
|
||
<li id="e4a8" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt lm le lf hf" data-selectable-paragraph="">Wait for input from the user
|
||
</li>
|
||
<li id="468b" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Data from a slow network connection, etc.
|
||
</li>
|
||
</ul>
|
||
<p id="5f6f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Let us call these software threads. Hardware threads mean you have actual physical CPU cores at your disposal to speed up things.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv nk">
|
||
<div class="jn s am jo">
|
||
<div class="oj jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="600" height="377" src="https://miro.medium.com/max/600/1*2mDUgCX9a49EldiCTbL6fA.png" srcset="https://miro.medium.com/max/276/1*2mDUgCX9a49EldiCTbL6fA.png 276w, https://miro.medium.com/max/552/1*2mDUgCX9a49EldiCTbL6fA.png 552w, https://miro.medium.com/max/600/1*2mDUgCX9a49EldiCTbL6fA.png 600w" sizes="600px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1200/1*2mDUgCX9a49EldiCTbL6fA.png" width="600" height="377" srcset="https://miro.medium.com/max/552/1*2mDUgCX9a49EldiCTbL6fA.png 276w, https://miro.medium.com/max/1104/1*2mDUgCX9a49EldiCTbL6fA.png 552w, https://miro.medium.com/max/1200/1*2mDUgCX9a49EldiCTbL6fA.png 600w" sizes="600px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</figure>
|
||
<p id="3d7f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The problem with threads is that software developers have to write so called multi-threaded code. That is often difficult. In the past, this was some of the hardest code to write. However making <em class="nh">server software</em> multi-threaded tends to be easy. It is simply a matter of handling each user request on a separate thread. Thus in this case having lots of cores, is an obvious advantage. Especially for cloud services.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div class="fu fv ok">
|
||
<div class="jn s am jo">
|
||
<div class="ol jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="358" height="309" src="https://miro.medium.com/max/358/1*X5ZTLTHUYBdw0t25TemHcQ.png" srcset="https://miro.medium.com/max/276/1*X5ZTLTHUYBdw0t25TemHcQ.png 276w, https://miro.medium.com/max/358/1*X5ZTLTHUYBdw0t25TemHcQ.png 358w" sizes="358px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/716/1*X5ZTLTHUYBdw0t25TemHcQ.png" width="358" height="309" srcset="https://miro.medium.com/max/552/1*X5ZTLTHUYBdw0t25TemHcQ.png 276w, https://miro.medium.com/max/716/1*X5ZTLTHUYBdw0t25TemHcQ.png 358w" sizes="358px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
The Ampere Altra Max ARM CPU with 128 cores designed for cloud computing, where a lot of hardware threads is a benefit.
|
||
</figcaption>
|
||
</figure>
|
||
<p id="f30f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
That is the reason why you see ARM CPU-makers such as Ampere making CPUs such as the <a href="https://www.networkworld.com/article/3564514/ampere-announces-128-core-arm-server-processor.html" class="ej ll" target="_blank" rel="noopener nofollow">Altra Max</a> which has a crazy 128 cores. This chip is specifically made for the cloud. You don’t need crazy single-core performance, because in the cloud it is all about having as many threads as possible per watt to handle as many concurrent users as possible.
|
||
</p>
|
||
<p id="e162" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Read more about ARM CPUs with many cores: <a href="https://erik-engheim.medium.com/are-servers-next-for-apple-7992213d72c9" class="ej ll" target="_blank" rel="noopener">Are Servers Next for Apple?</a>
|
||
</p>
|
||
<p id="6ead" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Apple, in contrast, is on the complete opposite end of the spectrum. They make single-user devices. Lots of threads is not an advantage. Their devices are used for gaming, video editing, development, etc. They want desktops with beautiful responsive graphics and animations.
|
||
</p>
|
||
<p id="e3ca" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Desktop software is generally not made to utilize lots of cores. For example, computer games will likely benefit from eight cores, but something like 128 cores would be a total waste. Instead, you would want fewer but more powerful cores.
|
||
</p>
|
||
<h2 id="8ac1" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
How Out-of-Order Execution Works
|
||
</h2>
|
||
<p id="4cc9" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
To make a more powerful core we need it to execute more instructions in parallel. <a href="https://en.wikipedia.org/wiki/Out-of-order_execution" class="ej ll" target="_blank" rel="noopener nofollow">Out-of-Order execution</a> (OoOE) is a way to execute more instructions in parallel but without exposing that capability as multiple threads.
|
||
</p>
|
||
<p id="4f36" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For an alternative solution read: <a href="https://erik-engheim.medium.com/very-long-instruction-word-microprocessors-17262def3037" class="ej ll" target="_blank" rel="noopener">Very Long Instruction Word Microprocessors</a>
|
||
</p>
|
||
<p id="db59" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Developers don’t have to code their software specifically to take advantage of OoOE. Seen from the developer’s perspective it just looks like each core runs faster. Please note it is not a direct alternative to hardware threads. You want to use both, depending on the particular problem you are solving.
|
||
</p>
|
||
<p id="2402" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
To understand how OoOE works, you need to understand some things about memory. Asking for data in one particular memory location is slow. But the CPU is capable of getting getting many bytes at the same time. Hence getting 1 specific byte in memory, takes no less time than getting 100 more bytes following that byte in memory.
|
||
</p>
|
||
<figure class="mo mp mq mr ms jd fu fv paragraph-image">
|
||
<div role="button" tabindex="0" class="je jf am jg v jh">
|
||
<div class="fu fv om">
|
||
<div class="jn s am jo">
|
||
<div class="on jq s">
|
||
<div class="fc ji er ff fb jj v jk jl jm"></div><img alt="Image for post" class="xl xm er ff fb jj v c" width="990" height="556" src="https://miro.medium.com/max/990/1*IbuGfelqOOtcyX8NwTh-tw.jpeg" srcset="https://miro.medium.com/max/276/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 276w, https://miro.medium.com/max/552/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 552w, https://miro.medium.com/max/640/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 640w, https://miro.medium.com/max/700/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 700w" sizes="700px" /><noscript><img alt="Image for post" class="er ff fb jj v" src="https://miro.medium.com/max/1980/1*IbuGfelqOOtcyX8NwTh-tw.jpeg" width="990" height="556" srcset="https://miro.medium.com/max/552/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 276w, https://miro.medium.com/max/1104/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 552w, https://miro.medium.com/max/1280/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 640w, https://miro.medium.com/max/1400/1*IbuGfelqOOtcyX8NwTh-tw.jpeg 700w" sizes="700px" /></noscript>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
</div>
|
||
<figcaption class="ju jv fw fu fv jw jx ba b bb bc dv" data-selectable-paragraph="">
|
||
Robot pickers in a Warehouse for Komplett.no, an online store in Norway
|
||
</figcaption>
|
||
</figure>
|
||
<p id="170f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Here is an analogy: Consider pickers in a warehouse. Could be the little red robots in the picture above. Moving to multiple locations spread all over takes time. But picking up items from slots adjacent to each other is quick. Computer memory is very similar. You can quickly fetch content of memory cells which are adjecent.
|
||
</p>
|
||
<p id="4d52" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Data is sent across what we call a databus. You can think of it as a road or pipe between memory and different parts of the CPU where data gets pushed through. In reality, it is of course just some copper tracks conducting electricity. If the databus is wide enough you can get multiple bytes at the same time.
|
||
</p>
|
||
<p id="2053" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Thus CPUs get a whole chunk of instructions at a time to execute. But they are written to be executed one after the other. Modern microprocessors do what we call Out-of-Order execution (OoOE).
|
||
</p>
|
||
<p id="de65" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
That means they are able to analyze a buffer of instructions quickly and see which ones depend on which. Look at the simple example below:
|
||
</p>
|
||
<pre class="mo mp mq mr ms mu mv mw"><span id="4de2" class="hf mx lo gi my b dl mz na s nb" data-selectable-paragraph="">01: mul r1, r2, r3 // r1 ← r2 × r3<br />02: add r4, r1, 5 // r4 ← r1 + 5<br />03: add r6, r2, 1 // r6 ← r2 + 1</span></pre>
|
||
<p id="d5a8" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Multiplication tends to be a slow process. So say it takes multiple clock cycles to perform. The second instruction will simply have to wait because its calculation depends on knowing the result that gets put into the <code class="jo nc nd ne my b">r1</code> register.
|
||
</p>
|
||
<p id="d3b8" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However, the third instruction at line <code class="jo nc nd ne my b">03</code> doesn’t depend on calculations from previous instructions. Hence an Out-of-Order processor can begin calculating this instruction in parallel.
|
||
</p>
|
||
<p id="deba" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However more realistically we are talking about hundreds of instructions. The CPU is able to figure out all the dependencies between these instructions.
|
||
</p>
|
||
<p id="b30b" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
It analyses the instructions by looking at the inputs to each instruction. Do the inputs depend on output from one or more other instructions? By input and output, we mean registers containing results from previous calculations.
|
||
</p>
|
||
<p id="d5b1" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For example, the <code class="jo nc nd ne my b">add r4, r1, 5</code> instruction depends on input from <code class="jo nc nd ne my b">r1</code> which is produced by <code class="jo nc nd ne my b">mul r1, r2, r3</code> . We can chain together these relationships into long elaborate graphs that the CPU can work through. The nodes are the instructions and the edges are the registers connecting them.
|
||
</p>
|
||
<p id="621d" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The CPU can analyze such a graph of nodes and determine which instructions it can perform in parallel and where it needs to wait for the results from multiple dependent calculations before carrying on.
|
||
</p>
|
||
<p id="46ee" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Many instructions will finish early but we cannot make their results official. We cannot commit them; otherwise, we supply the result in the wrong order. To the rest of the world, it has to look as if the instructions were carried out in the same sequence as they were issued.
|
||
</p>
|
||
<p id="8815" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Like a stack, the CPU will keep popping done instructions from the top, until hitting an instruction that is not done.
|
||
</p>
|
||
<p id="0770" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Basically you got two forms of parallelism: One that the developer must deal with explicitly when writing code and one that is entirely transparent. Of course the latter relies on lots of transistors on the CPU dedicated to Out-of-Order Execution magic. This is not a viable solution for small CPUs with few transistors.
|
||
</p>
|
||
<p id="01ee" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
It is the superior Out-of-Order execution that is making the Firestorm cores on the M1 kick ass and take names. It is in fact much stronger than anything from Intel or AMD and they may never be able to catch up. To understand why, we need to get into some more technical details.
|
||
</p>
|
||
<h2 id="52fe" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
ISA Instructions vs Micro-Operations
|
||
</h2>
|
||
<p id="c057" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
Previously I skipped some details on how Out-of-Order Execution (OoOE) works.
|
||
</p>
|
||
<p id="5a6b" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Programs loaded into memory are made up of machine code instructions designed for specific Instruction-Set Architectures (ISA) such as x86, ARM, PowerPC, 68K, MIPS, AVR etc.
|
||
</p>
|
||
<p id="c8b7" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For instance the x86 instruction to fetch a number from memory location 24 into a register you may write:
|
||
</p>
|
||
<pre class="mo mp mq mr ms mu mv mw"><span id="bc03" class="hf mx lo gi my b dl mz na s nb" data-selectable-paragraph="">MOV ax, 24</span></pre>
|
||
<p id="c6bc" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
x86 have registers named <code class="jo nc nd ne my b">ax</code>, <code class="jo nc nd ne my b">bx</code>, <code class="jo nc nd ne my b">cx</code> and <code class="jo nc nd ne my b">dx</code>(remember these are the memory cells inside the CPU you perform operations on). However the equivalent ARM instruction would look like this:
|
||
</p>
|
||
<pre class="mo mp mq mr ms mu mv mw"><span id="64d0" class="hf mx lo gi my b dl mz na s nb" data-selectable-paragraph="">LDR r0, 24</span></pre>
|
||
<p id="4cd1" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
AMD and Intel processors understand the x86 ISA, while Apple Silicon chips, such as M1, understand the ARM Instruction-Set Architecture (ISA).
|
||
</p>
|
||
<p id="2266" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However internally the CPU works on an entirely different instruction-set invisible to the programmer. We call these micro-operations (micro-ops or μops). These are the instructions the Out-of-Order hardware works with.
|
||
</p>
|
||
<p id="a998" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
But why can’t the OoOE hardware work with regular machine code instructions? Because the CPU needs to attach lots of different information to the instructions to be able to run them in parallel.
|
||
</p>
|
||
<p id="8d96" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Thus while a normal ARM instruction may be 32-bit (32 digits of 0 and 1), a micro-op can be much longer. It contains information about its order.
|
||
</p>
|
||
<pre class="mo mp mq mr ms mu mv mw"><span id="a55d" class="hf mx lo gi my b dl mz na s nb" data-selectable-paragraph="">01: mul r1, r2, r3 // r1 ← r2 × r3<br />02: add r4, r1, 5 // r4 ← r1 + 5<br />03: add r1, r2, 1 // r1 ← r2 + 1</span></pre>
|
||
<p id="0c5e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Consider if we run instruction <code class="jo nc nd ne my b">01: mul</code> and <code class="jo nc nd ne my b">03: add</code> in parallel. Both store their result in register <code class="jo nc nd ne my b">r1</code> . If we write the result of instruction <code class="jo nc nd ne my b">03: add</code> before <code class="jo nc nd ne my b">01: mul</code>, then instruction <code class="jo nc nd ne my b">02: add</code> will get the wrong input. Hence it is very important to keep track of instruction order. The order is stored with each micro-op. It also stores e.g. that instruction <code class="jo nc nd ne my b">02: add</code> depends on output from <code class="jo nc nd ne my b">01: mul</code>.
|
||
</p>
|
||
<p id="64b5" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
That is why we cannot have programs written using micro-ops. They contain lots of details specific to the internals of each microprocessor. Two ARM processors could have very different micro-ops internally.
|
||
</p>
|
||
<p id="31fb" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Read more about CPUs with micro-ops like instructions: <a href="https://erik-engheim.medium.com/very-long-instruction-word-microprocessors-17262def3037" class="ej ll" target="_blank" rel="noopener">Very Long Instruction Word Microprocessors.</a>
|
||
</p>
|
||
<p id="3180" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Also, micro-ops are usually easier to work with for the CPU. Why? Because they each do <em class="nh">one</em> simple limited task. Regular ISA instructions can be more complex causing a bunch of stuff to happen and thus frequently translate to multiple micro-ops. Thus the name “micro” comes from the small task they do, not the length of the instruction in memory.
|
||
</p>
|
||
<p id="ff1f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
For CISC CPUs there is usually no alternative but to use micro-ops otherwise the large complex CISC instructions would make pipelines and OoOE next to impossible to achieve.
|
||
</p>
|
||
<p id="4d71" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Read more: <a href="https://erik-engheim.medium.com/microprocessor-pipelining-f63df4ee60cf" class="ej ll" target="_blank" rel="noopener">Why Pipeline a Microprocessor?</a>
|
||
</p>
|
||
<p id="9da7" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
RISC CPUs have a choice. So, for example, smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoOE.
|
||
</p>
|
||
</div>
|
||
</div>
|
||
</section>
|
||
<div class="n p cx oo op oq" role="separator"></div>
|
||
<section class="gb gc gd ds ge">
|
||
<div class="n p">
|
||
<div class="ao ap aq ar as gf au v">
|
||
<h2 id="b27b" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
Why is AMD and Intel Out-of-Order execution inferior to M1?
|
||
</h2>
|
||
<p id="cd20" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
But you wonder, why does any of this matter? Why is this detail important to know to understand why Apple has the upper hand on AMD and Intel?
|
||
</p>
|
||
<p id="8286" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
It is because the ability to run fast depends on how quickly you can fill up a buffer of micro-operations. If you got a large buffer then the OoOE hardware will have an easier time to locate two or more instructions which it can run in parallel. But there is no point in having a large instruction buffer if you cannot refill it fast enough after instructions get picked and executed.
|
||
</p>
|
||
<p id="5cf7" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The ability to refill the instruction buffer quickly relies on the ability to quickly chop machine code instruction into micro-ops. The hardware units that does this are called <em class="nh">decoders</em>.
|
||
</p>
|
||
<p id="d0d8" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
And finally we get to the killer feature of the M1. The biggest and meanest Intel and AMD microprocessor have a total of four decoders busy cutting machine code instructions into micro-ops.
|
||
</p>
|
||
<p id="8622" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
But this is no match for the M1, which has an absolutely unheard of number of decoders: Eight. Significantly more than anybody else in the industry. That means it can fill up the instruction buffer much quicker.
|
||
</p>
|
||
<p id="0669" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
To deal with this the M1 also has an instruction buffer which is 3x times larger than what is normal in the industry.
|
||
</p>
|
||
<h2 id="59ff" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
Why can’t Intel and AMD add more instruction decoders?
|
||
</h2>
|
||
<p id="4735" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
This is where we finally see the revenge of RISC, and where the fact that the M1 Firestorm core has an ARM RISC architecture begins to matter.
|
||
</p>
|
||
<p id="fca4" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
You see, an x86 instruction can be anywhere from 1–15 bytes long. RISC instructions have fixed length. Every ARM instruction is 4 bytes long. Why is that relevant in this case?
|
||
</p>
|
||
<p id="d102" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Because splitting up a stream of bytes into instructions to feed into eight different decoders in parallel becomes trivial if every instruction has the same length.
|
||
</p>
|
||
<p id="b4e4" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However, on an x86 CPU, the decoders have no clue <em class="nh">where</em> the next instruction starts. It has to actually analyze each instruction in order to see how long it is.
|
||
</p>
|
||
<p id="e842" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
The brute force way Intel and AMD deal with this is by simply attempting to decode instructions at every possible starting point. That means x86 chips have to deal with lots of wrong guesses and mistakes which has to be discarded. This creates such a convoluted and complicated decoder stage that it is really hard to add more decoders. But for Apple, it is trivial in comparison to keep adding more.
|
||
</p>
|
||
<p id="499d" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
In fact, adding more causes so many other problems that four decoders according to AMD itself is basically an upper limit for them.
|
||
</p>
|
||
<p id="bb2e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
<mark class="xs xt ew">This is what allows the M1 Firestorm cores to essentially process</mark> <mark class="xs xt ew"><strong class="ka ov">twice</strong></mark> <mark class="xs xt ew">as many instructions as AMD and Intel CPUs at the</mark> <mark class="xs xt ew"><em class="nh">same</em></mark> <mark class="xs xt ew">clock frequency.</mark>
|
||
</p>
|
||
<p id="327e" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
One could argue as a counterpoint that CISC instructions turn into more micro-ops. For instance if every x86 instruction turned into 2 micro-ops while every ARM instruction turned into 1 micro-op, then four x86 decoders would produce the same number of micro-ops per clock cycle as an ARM CPU with 8 decoders.
|
||
</p>
|
||
<p id="b2f1" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
Except this is not the case in the real world. Highly optimized x86 code rarely uses complex CISC instructions, which would translate into many micro-ops. In fact most will only translate into 1 micro-op.
|
||
</p>
|
||
<p id="8792" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
However all these simple x86 instructions don’t help Intel or AMD. Because even if those 15 byte long instructions are rare, the decoders have to be made to handle them. This incurs complexity that blocks AMD and Intel from adding more decoders.
|
||
</p>
|
||
<h2 id="26e4" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
But AMDs Zen3 cores are still faster right?
|
||
</h2>
|
||
<p id="7106" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
As far as I remember from performance benchmarks, the newest AMD CPU cores, the ones called Zen3 are slightly faster than Firestorm cores. But here is the kicker: That only happens because the Zen3 cores are clocked at 5 GHz. Firestorm cores are clocked at 3.2 GHz. The Zen3 is just barely squeezing past Firestorm despite having almost 60% higher clock frequency.
|
||
</p>
|
||
<p id="da9f" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
So why doesn’t Apple increase the clock frequency too? Because higher clock frequency makes the chips run hotter. That is one of Apple’s key selling points. Their computers — unlike Intel and AMD offerings — barely need cooling.
|
||
</p>
|
||
<p id="f640" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
In essence, one could say Firestorm cores really are superior to Zen3 cores. Zen3 only manages to stay in the game by drawing a lot more current and getting a lot hotter. Something Apple simply chooses not to do.
|
||
</p>
|
||
<p id="6302" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt gb hf" data-selectable-paragraph="">
|
||
If Apple wants higher performance they are simply going to add more cores. That lets them keep watt usage down while offering more performance.
|
||
</p>
|
||
<h2 id="e95d" class="mx lo gi ba lp no np hj ls nq nr hm lv hn ns hp lz hq nt hs md ht nu hv mh nv hf" data-selectable-paragraph="">
|
||
The future
|
||
</h2>
|
||
<p id="9450" class="jy jz gi ka b hh mj kc kd hk mk kf kg kh ml kj kk kl mm kn ko kp mn kr ks kt gb hf" data-selectable-paragraph="">
|
||
It seems AMD and Intel have painted themselves into a corner on two fronts:
|
||
</p>
|
||
<ul class="">
|
||
<li id="9af9" class="jy jz gi ka b hh kb kc kd hk ke kf kg kh ki kj kk kl km kn ko kp kq kr ks kt lm le lf hf" data-selectable-paragraph="">They don’t have a business model that makes it easy to pursue heterogeneous computing and SoC designs.
|
||
</li>
|
||
<li id="7c75" class="jy jz gi ka b hh lg kc kd hk lh kf kg kh li kj kk kl lj kn ko kp lk kr ks kt lm le lf hf" data-selectable-paragraph="">Their legacy x86 CISC instruction set is coming back to haunt them, making it hard to improve OoO performance.
|
||
</li>
|
||
</ul>
|
||
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Read more: <a href="https://erik-engheim.medium.com/intel-arm-and-the-innovators-dilemma-a9ebd20ea200" class="ej ll" target="_blank" rel="noopener">Intel, ARM and the Innovators Dilemma</a>
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It doesn’t mean game over. They can increase the clock frequency and use more cooling, throw in more cores, beef up the CPU caches, etc. But they are both at a disadvantage. Intel is in the worst situation, as their cores are already soundly beaten by Firestorm, and they have weak GPUs to integrate with an SoC solution.
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The problem with throwing in more cores is that for typical desktop workloads you reach diminishing returns with too many cores. Sure lots of cores are great for servers.
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However here companies such as Amazon and Ampere are attacking with monster CPUs with 128 cores. This is like fighting the western and eastern front at the same time.
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But fortunately for AMD and Intel, Apple doesn’t sell their chips on the market. So PC users will simply have to put up with whatever they are offering. PC users may jump ship, but that is a slow process. You don’t leave immediately a platform you are heavily invested in.
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But young professionals, with money to burn without too deep investments in any platform, may increasingly turn to Apple in the future, beefing up their hold on the premium market and consequently their share of the total profit in the PC market.
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<ul class="ce cf">
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<a href="/tagged/m1" class="ba b sg sh dv si sj bw s mv">M1</a>
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<a href="/tagged/apple-silicon" class="ba b sg sh dv si sj bw s mv">Apple Silicon</a>
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<a href="https://debugger.medium.com/?source=follow_footer-------------------------------------" class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener">More from Debugger</a>
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Debugger is a publication from Medium about consumer technology and gadgets. It is run by the OneZero editorial team, which also publishes stories about major forces in technology through its namesake publication and stories about science on Future Human.
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<span class="ba b bb bc hf">Damon Beres</span>
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<span class="ba b bb bc dv"><span class="im">·</span>Nov 25, 2020</span>
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<a class="ej bw" rel="noopener" href="/even-if-we-cant-be-together-we-can-stop-delivering-terrible-holiday-gifts-37cbb8bad808?source=follow_footer---------0----------------------------">“Even if we can’t be together, we can stop delivering terrible holiday gifts”</a>
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</h1>
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<p id="240c" class="jy jz gi ka b hh kc kd hk kf kg kh kj kk kl kn ko kp kr ks aee kt gb hf" data-selectable-paragraph="">
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With Black Friday upon us, <a href="https://medium.com/@LanceUlanoff/what-not-to-buy-on-black-friday-pandemic-edition-9b179b5aa926" class="ej ll" target="_blank" rel="noopener">tech writer Lance Ulanoff has wisdom to share</a> about the presents to avoid. Why are stores still hawking DVD players and Blu-Ray discs? And $25 Apple Watch knockoffs? Don’t fall for any of it.
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Read the full story at the link below:
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<a href="https://medium.com/@LanceUlanoff/what-not-to-buy-on-black-friday-pandemic-edition-9b179b5aa926" target="_blank" rel="noopener">
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What Not to Buy on Black Friday Pandemic Edition
|
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<h3 class="ba b dl bc jk aek tc td ael tf tg dv">
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Even if we can’t be together, we can stop delivering terrible holiday gifts
|
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</h3>
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medium.com
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<button class="ej ek bz ca cb cc cd ce cf bl el em cg en eo">43</button>
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<h4 class="ba b bb bc dv">
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<span class="ba b bb bc dv"><span class="im">·</span>Nov 25, 2020<svg class="ij ik il" width="15" height="15" viewbox="0 0 15 15">
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<a class="ej bw" rel="noopener" href="/how-to-optimize-your-ability-to-focus-with-sound-and-music-b59731128be8?source=follow_footer---------1----------------------------">How to Optimize Your Ability to Focus With Sound and Music</a>
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What science and experts say is the best music for tuning out the world while working through a pandemic
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Photo: Gabriel Chalmeta/500px/Getty Images
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Last week, an Eminem <a href="https://www.youtube.com/watch?v=0-9mDUCEzQM&feature=emb_title" class="ej ll" target="_blank" rel="noopener nofollow">YouTube video</a> made me sick.
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Not because of anything Eminem did, but rather because the song that streamed when I clicked play is edited into what’s known as “8D audio,” a <a href="https://www.digitaltrends.com/home-theater/what-is-8d-audio/" class="ej ll" target="_blank" rel="noopener nofollow">nonsense term</a> that describes music that’s been modulated to sound as if it’s playing in your shared physical space. Eminem’s voice, for example, was edited to play gradually louder in my left earphone — as if he was approaching me from the left as he raps, before his voice circled around to my right.
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8D audio is frequently promoted as <a href="https://www.youtube.com/results?search_query=8d+sounds+for+focus" class="ej ll" target="_blank" rel="noopener nofollow">great for focus</a>, though the notion that someone would find it easier to concentrate while sitting in the same room as, say, a dubstep artist is beyond me. Research suggests you should dispense with distracting 8D audio and listen to another type of music or sound instead. …
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<h4 class="ba b bb bc fl">
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Read more · 8 min read
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<span class="ba b bb bc dv"><span class="im">·</span>Nov 25, 2020<svg class="ij ik il" width="15" height="15" viewbox="0 0 15 15">
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<a class="ej bw" rel="noopener" href="/replace-your-face-with-an-a-i-twin-to-trick-facial-recognition-22be6931cf1?source=follow_footer---------2----------------------------">Replace Your Face With an A.I. Twin to Trick Facial Recognition</a>
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If you’ve posted a photo of yourself online in the past few years, there’s a good chance Clearview AI has slurped it up and added it to the company’s massive facial recognition database of more than 3.1 billion images. The <em class="nh">New York Times</em> said that Clearview could “<a href="https://www.nytimes.com/2020/01/18/technology/clearview-privacy-facial-recognition.html" class="ej ll" target="_blank" rel="noopener nofollow">end privacy as we know it</a>.” In January, I got my hands on my own Clearview AI profile, and <a href="https://onezero.medium.com/i-got-my-file-from-clearview-ai-and-it-freaked-me-out-33ca28b5d6d4" class="ej ll" target="_blank" rel="noopener">its contents freaked me out</a>.
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A wide variety of legal and legislative challenges have been mounted against Clearview. My own article was cited in the American Civil Liberties Union’s <a href="https://www.aclu.org/sites/default/files/field_document/aclu_v_clearview_complaint_final.pdf" class="ej ll" target="_blank" rel="noopener nofollow">landmark class-action lawsuit</a> against the company. …
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<h4 class="ba b bb bc fl">
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Read more · 8 min read
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<span class="ba b bb bc hf">Thomas Smith</span>
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</h4></a></span>
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</div><span class="ba b bb bc dv"><a class="" rel="noopener" href="/a-gift-guide-to-this-holiday-seasons-creepiest-surveillance-gadgets-d46a65fcd53e?source=follow_footer---------3----------------------------">
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<h4 class="ba b bb bc dv">
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<span class="ba b bb bc dv"><span class="im">·</span>Nov 24, 2020<svg class="ij ik il" width="15" height="15" viewbox="0 0 15 15">
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<h2 id="d29c" class="afx afy gi ba b sg tr nv dv pk" data-selectable-paragraph="">
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<a href="https://debugger.medium.com/tagged/gift-guide" class="ej bw" target="_blank" rel="noopener">Gift Guide</a>
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<div class="">
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<h1 id="ef1a" class="gg gh gi gj b lq kc ls lt kf lv acv acw acx acy acz aea aeb aec aed aem he hf">
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<a class="ej bw" rel="noopener" href="/a-gift-guide-to-this-holiday-seasons-creepiest-surveillance-gadgets-d46a65fcd53e?source=follow_footer---------3----------------------------">A Gift Guide to This Holiday Season’s Creepiest Surveillance Gadgets</a>
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</h1>
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</div>
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<div class="">
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<h2 id="4383" class="hg gh gi ba b afq afr hw hh hj hk hm hn hp hq hs ht hv dv">
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Let your loved ones decide what privacy means to them
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<img alt="3 different web cams facing a little figurine person." class="er ff fb jj v jr js jt" src="https://miro.medium.com/max/30/0*qDA-p6tROLkwpN1E?q=20" width="700" height="467" />
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</div><img alt="3 different web cams facing a little figurine person." class="fc ji er ff fb jj v c" width="700" height="467" />
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Photo courtesy of the author
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One of the best things about the holiday season is that you get to force your own privacy preferences on others.
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</p>
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<p id="274e" class="jy jz gi ka b hh kc kd hk kf kg kh kj kk kl kn ko kp kr ks aef kt gb hf" data-selectable-paragraph="">
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Maybe your family member wouldn’t normally buy a watch that tells Google when they’re asleep or a doorbell that helps them inform on their neighbors. But during this brief window each year, you can make a whole variety of fraught privacy decisions for them through gift-giving! They’ll be forced to live with your privacy choices or risk offending you by returning your thoughtful, pricey gadget to the Amazon warehouse from whence it came.
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</p>
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You love your friends and family. Really, you do. But if your gadget choice allowed a soulless megacorporation to siphon up their personal data to feed its ever-churning grist mill of profit, maybe you’d be okay with that. Or perhaps you’d enjoy the option of remotely flying a surveillance drone around their home — or activating the camera on their smart assistant by “dropping in” without their immediate consent. …
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<a class="ej ek bz ca cb cc cd ce cf bl el em cg en eo" rel="noopener" href="/a-gift-guide-to-this-holiday-seasons-creepiest-surveillance-gadgets-d46a65fcd53e?readmore=1&source=follow_footer---------3----------------------------">
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<h4 class="ba b bb bc fl">
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Read more · 9 min read
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<span class="ba b bb bc hf"><a href="https://megan.medium.com/?source=follow_footer---------4----------------------------" class="" rel="noopener">
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<h4 class="ba b bb bc fl">
|
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<span class="ba b bb bc hf">Megan Morrone</span>
|
||
</h4></a></span>
|
||
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|
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</div><span class="ba b bb bc dv"><a class="" rel="noopener" href="/watch-charlies-brown-s-holiday-specials-without-an-apple-tv-subscription-in-this-limited-window-44c9d2e3ef38?source=follow_footer---------4----------------------------">
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<h4 class="ba b bb bc dv">
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<span class="ba b bb bc dv"><span class="im">·</span>Nov 24, 2020<svg class="ij ik il" width="15" height="15" viewbox="0 0 15 15">
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<path d="M7.44 2.32c.03-.1.09-.1.12 0l1.2 3.53a.29.29 0 0 0 .26.2h3.88c.11 0 .13.04.04.1L9.8 8.33a.27.27 0 0 0-.1.29l1.2 3.53c.03.1-.01.13-.1.07l-3.14-2.18a.3.3 0 0 0-.32 0L4.2 12.22c-.1.06-.14.03-.1-.07l1.2-3.53a.27.27 0 0 0-.1-.3L2.06 6.16c-.1-.06-.07-.12.03-.12h3.89a.29.29 0 0 0 .26-.19l1.2-3.52z"></path></svg></span>
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<a class="ej bw" rel="noopener" href="/watch-charlies-brown-s-holiday-specials-without-an-apple-tv-subscription-in-this-limited-window-44c9d2e3ef38?source=follow_footer---------4----------------------------">Watch Charlie’s Brown’s Holiday Specials Without an Apple TV+ Subscription (In This Limited Window)</a>
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<p id="52b1" class="jy jz gi ka b hh kc kd hk kf kg kh kj kk kl kn ko kp kr ks aee kt gb hf" data-selectable-paragraph="">
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We can’t gather safely with all of our loved ones this year, but thanks to Apple, we can now watch <em class="nh">A Charlie Brown Thanksgiving</em> without an Apple TV+ subscription. So, I guess we have something to be sort of grateful for?
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Last month <a class="ej ll" target="_blank" rel="noopener" href="/were-being-privatized-charlie-brown-5674a623899a"><em class="nh">Debugger</em> reported</a> that, for the first time ever, the classic Peanuts holiday specials would stream exclusively on Apple TV+ and would be available only to those willing to pay the $4.99 a month subscription or sign up for one of the <a class="ej ll" target="_blank" rel="noopener" href="/apple-one-wants-you-to-pay-more-to-bundle-services-you-dont-want-ee81ad776f62">Apple One bundles</a>. Not exactly in the spirit of these anti-capitalistic children’s stories.
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<p id="4cfe" class="jy jz gi ka b hh kc kd hk kf kg kh kj kk kl kn ko kp kr ks aef kt gb hf" data-selectable-paragraph="">
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Now, <a href="https://variety.com/2020/tv/news/charlie-brown-pbs-apple-peanuts-tv-streaming-1234834757/" class="ej ll" target="_blank" rel="noopener nofollow">according to <em class="nh">Variety</em></a>, Apple will share the Peanuts gang’s misadventures, including Charlie’s beautiful tiny tree with the rest of us. <em class="nh">A Charlie Brown Thanksgiving</em> aired on PBS last night, but anyone can watch it for free with the Apple TV+ app (or via the web portal for those without an Apple device) from November 25–27. You can watch <em class="nh">A Charlie Brown Christmas</em> the same way from December 11–13. …
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<h4 class="ba b bb bc fl">
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Read more · 1 min read
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<a href="https://debugger.medium.com/?source=follow_footer-------------------------------------" class="ba b bb bc dz be ea eb ec ed ee bl bm bn ef eg br bs bt bu bv bw" rel="noopener">Read more from <!-- -->Debugger</a>
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||
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||
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||
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It is run by the OneZero editorial team, which also publishes stories about major forces in technology through its namesake publication and stories about science on Future Human.","ampEnabled":false,"twitterUsername":null,"facebookPageId":null},"User:c2fa2c34f40c":{"id":"c2fa2c34f40c","__typename":"User","isSuspended":false,"name":"Erik Engheim","hasCompletedProfile":false,"bio":"Geek dad, living in Oslo, Norway with passion for UX, Julia programming, science, teaching, reading and writing.","imageId":"0*1Y9ylHZ8csOxgZr7.jpg","customStyleSheet":null,"hasDomain":true,"username":"erik-engheim","isAuroraVisible":true,"socialStats":{"__typename":"SocialStats","followerCount":6714},"isBlocking":false,"mediumMemberAt":1563174000000,"isMuting":false,"isFollowing":false,"allowNotes":true,"newsletterV3":null,"viewerIsUser":false,"twitterScreenName":"","isPartnerProgramEnrolled":false},"ImageMetadata:1*s3Uiw9sGrwFiIayL4hge0A.png":{"id":"1*s3Uiw9sGrwFiIayL4hge0A.png","__typename":"ImageMetadata","originalWidth":2880},"ImageMetadata:1*fHP0sKfxxIHwAV-ADLsQlg.png":{"id":"1*fHP0sKfxxIHwAV-ADLsQlg.png","__typename":"ImageMetadata","originalWidth":2000,"originalHeight":422},"Paragraph:6df80d920455_0":{"id":"6df80d920455_0","__typename":"Paragraph","name":"8c58","text":"Why Is Apple’s M1 Chip So Fast?","type":"H3","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_1":{"id":"6df80d920455_1","__typename":"Paragraph","name":"d808","text":"Real-world experience with the new M1 Macs has started ticking in. They are fast. Real fast. But why? What is the magic?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_2":{"id":"6df80d920455_2","__typename":"Paragraph","name":"70b3","text":"Image: Apple","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*thz7gKafCYxWoA0h8aGjcg.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_3":{"id":"6df80d920455_3","__typename":"Paragraph","name":"8eb8","text":"On YouTube, I watched a Mac user who had bought an iMac last year. It was maxed out with 40 GB of RAM costing him about $4,000. He watched in disbelief how his hyperexpensive iMac was being demolished by his new M1 Mac Mini, which he had paid a measly $700 for.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":true,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_4":{"id":"6df80d920455_4","__typename":"Paragraph","name":"1408","text":"In real-world test after test, the M1 Macs are not merely inching past top-of-the-line Intel Macs, they are destroying them. In disbelief, people have started asking how on earth this is possible?","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_5":{"id":"6df80d920455_5","__typename":"Paragraph","name":"71b6","text":"If you are one of those people, you have come to the right place. Here I plan to break it down into digestible pieces exactly what it is that Apple has done with the M1. Specifically the questions I think a lot of people have are:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_6":{"id":"6df80d920455_6","__typename":"Paragraph","name":"89bf","text":"What are the technical reasons this M1 chip is so fast?","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_7":{"id":"6df80d920455_7","__typename":"Paragraph","name":"c5cb","text":"Has Apple made some really exotic technical choices to make this possible?","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_8":{"id":"6df80d920455_8","__typename":"Paragraph","name":"03e6","text":"How easy will it be for the competition such as Intel and AMD to pull the same technical tricks?","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_9":{"id":"6df80d920455_9","__typename":"Paragraph","name":"6e93","text":"Sure you could try to Google this, but if you try to learn what Apple has done beyond the superficial explanations, you will quickly get buried in highly technical jargon such as M1 using very wide instruction decoders, enormous reorder buffer (ROB), etc. Unless you are a CPU hardware geek, a lot of this will simply be gobbledygook.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_10":{"id":"6df80d920455_10","__typename":"Paragraph","name":"ecc7","text":"To get the most out of this story I advise reading my earlier piece: “What Does RISC and CISC mean in 2020?” There I explain what a microprocessor (CPU) is as well as various important concepts such as:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":70,"end":106,"type":"A","href":"https:\u002F\u002Fmedium.com\u002Fswlh\u002Fwhat-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_11":{"id":"6df80d920455_11","__typename":"Paragraph","name":"4638","text":"Instruction set architecture (ISA)","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_12":{"id":"6df80d920455_12","__typename":"Paragraph","name":"e7aa","text":"Pipelining","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_13":{"id":"6df80d920455_13","__typename":"Paragraph","name":"69ae","text":"Load\u002Fstore architecture","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_14":{"id":"6df80d920455_14","__typename":"Paragraph","name":"f37f","text":"Microcode vs. micro-operations","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_15":{"id":"6df80d920455_15","__typename":"Paragraph","name":"85a3","text":"But if you are impatient, I will do a quick version of the material you need to understand to grasp my explanation of the M1 chip.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_16":{"id":"6df80d920455_16","__typename":"Paragraph","name":"a207","text":"What is a microprocessor (CPU)?","type":"H3","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_17":{"id":"6df80d920455_17","__typename":"Paragraph","name":"285c","text":"Normally when speaking of chips from Intel and AMD we talk about central processing units (CPUs) or microprocessors. As you can read more about in my RISC vs. CISC story, these pull in instructions from memory. Then each instruction is typically carried out in sequence.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":150,"end":169,"type":"A","href":"https:\u002F\u002Fmedium.com\u002Fswlh\u002Fwhat-does-risc-and-cisc-mean-in-2020-7b4d42c9a9de","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_18":{"id":"6df80d920455_18","__typename":"Paragraph","name":"a711","text":"A very basic RISC CPU, not the M1. Instructions are moved from memory along blue arrows into the instruction register. There a decoder figures out what the instruction is and enables different parts of the CPU through the red control lines. The ALU adds and subtracts numbers placed in the registers.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*3G7uz4l1GnFacxz6InrLLw.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":76,"end":80,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":222,"end":225,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_19":{"id":"6df80d920455_19","__typename":"Paragraph","name":"5525","text":"A CPU at its most basic level is a device with a number of named memory cells called registers and a number of computational units called arithmetic logic units (ALU). The ALUs perform things like addition, subtraction, and other basic math operations. However, these are only connected to the CPU registers. If you want to add up two numbers, you have to get those two numbers from memory and into two registers in the CPU.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_20":{"id":"6df80d920455_20","__typename":"Paragraph","name":"db6e","text":"Here are some examples of typical instructions that a RISC CPU as found on the M1 carries out.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_21":{"id":"6df80d920455_21","__typename":"Paragraph","name":"9500","text":"load r1, 150\nload r2, 200\nadd r1, r2\nstore r1, 310","type":"PRE","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":0,"end":51,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_22":{"id":"6df80d920455_22","__typename":"Paragraph","name":"d5bb","text":"Here r1 and r2 are the registers I talked about. Modern RISC CPUs cannot do operations on numbers that are not in a register like this. For example, it cannot add two numbers residing in RAM in two different locations. Instead, it has to pull these two numbers into a separate register. That is what we do in this simple example. We pull in the number at memory location 150 in the RAM and put it into register r1 in the CPU. Next, we put the contents of address 200 into register r2. Only then can the numbers be added with the add r1, r2 instruction.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":5,"end":7,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":12,"end":14,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":411,"end":413,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":481,"end":483,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":529,"end":539,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_23":{"id":"6df80d920455_23","__typename":"Paragraph","name":"7d8c","text":"An old mechanical calculator with two registers: the accumulator and input register. Modern CPUs typically have more than a dozen registers, and they are electronic rather than mechanical.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*kDqSqtumOzNFZdpixUW0IQ.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_24":{"id":"6df80d920455_24","__typename":"Paragraph","name":"7146","text":"The concept of registers is old. For example, on this old mechanical calculator, the register is what holds the numbers you are adding. Likely the origin of the term cash register. The register is where you registered input numbers.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":85,"end":93,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":166,"end":179,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_25":{"id":"6df80d920455_25","__typename":"Paragraph","name":"22f2","text":"The M1 is not a CPU!","type":"H3","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_26":{"id":"6df80d920455_26","__typename":"Paragraph","name":"d450","text":"But here is a very important thing to understand about the M1:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_27":{"id":"6df80d920455_27","__typename":"Paragraph","name":"777f","text":"The M1 is not a CPU, it is a whole system of multiple chips put into one large silicon package. The CPU is just one of these chips.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_28":{"id":"6df80d920455_28","__typename":"Paragraph","name":"69f0","text":"Basically, the M1 is one whole computer onto a chip. The M1 contains a CPU, graphical processing unit (GPU), memory, input and output controllers, and many more things making up a whole computer. This is what we call a system on a chip (SoC).","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_29":{"id":"6df80d920455_29","__typename":"Paragraph","name":"2be5","text":"M1 is a system on a chip. Meaning all the parts making up a computer are placed on one silicon chip.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*c4EYUAVj4k7n6wWLoWUVdA.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_30":{"id":"6df80d920455_30","__typename":"Paragraph","name":"fce1","text":"Today if you buy a chip — whether from Intel or AMD — you actually get what amounts to multiple microprocessors in one package. In the past computers would have multiple physically separate chips on the motherboard of the computer.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":87,"end":95,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_31":{"id":"6df80d920455_31","__typename":"Paragraph","name":"2ec0","text":"Example of a computer motherboard. Memory, CPU, graphics cards, IO controllers, network cards, and many other components can be attached to the motherboard to communicate with each other.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*GBrG4D2YCEVYREXAHIiJnQ.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_32":{"id":"6df80d920455_32","__typename":"Paragraph","name":"9cf5","text":"However because we are able to put so many transistors on a silicon die today, companies such as Intel and AMD began putting multiple microprocessors onto one chip. Today we refer to these chips as CPU cores. One core is basically a full independent chip that can read instructions from memory and perform calculations.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_33":{"id":"6df80d920455_33","__typename":"Paragraph","name":"5d80","text":"A microchip with multiple CPU cores.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*XZsBJV_v4WybnUFYjJJiPQ.gif"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_34":{"id":"6df80d920455_34","__typename":"Paragraph","name":"18a4","text":"This has for a long time been the name of the game in terms of increasing performance: Just add more general-purpose CPU cores. But there is a disturbance in the force. There is one player in the CPU market which is deviating from this trend.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_35":{"id":"6df80d920455_35","__typename":"Paragraph","name":"cff4","text":"Apple’s not so secret heterogeneous computing strategy","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_36":{"id":"6df80d920455_36","__typename":"Paragraph","name":"8feb","text":"Instead of adding ever more general-purpose CPU cores, Apple has followed another strategy: They have started adding ever more specialized chips doing a few specialized tasks. The benefit of this is that specialized chips tend to be able to perform their tasks significantly faster using much less electric current than a general-purpose CPU core.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_37":{"id":"6df80d920455_37","__typename":"Paragraph","name":"e379","text":"This is not entirely new knowledge. For many years already specialized chips such as the graphical processing units (GPUs) have been sitting in Nvidia and AMD graphics cards performing operations related to graphics much faster than general-purpose CPUs.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_38":{"id":"6df80d920455_38","__typename":"Paragraph","name":"866e","text":"What Apple has done is simply to take a more radical shift toward this direction. Rather than just having general-purpose cores and memory, the M1 contains a wide variety of specialized chips:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_39":{"id":"6df80d920455_39","__typename":"Paragraph","name":"6e0e","text":"Central processing unit (CPU) — the “brains” of the SoC. Runs most of the code of the operating system and your apps.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_40":{"id":"6df80d920455_40","__typename":"Paragraph","name":"037c","text":"Graphics processing unit (GPU) — handles graphics-related tasks, such as visualizing an app’s user interface and 2D\u002F3D gaming.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_41":{"id":"6df80d920455_41","__typename":"Paragraph","name":"9a44","text":"Image processing unit (ISP) — can be used to speed up common tasks done by image processing applications.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_42":{"id":"6df80d920455_42","__typename":"Paragraph","name":"c654","text":"Digital signal processor (DSP) — handles more mathematically intensive functions than a CPU. Includes decompressing music files.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_43":{"id":"6df80d920455_43","__typename":"Paragraph","name":"1cac","text":"Neural processing unit (NPU) — used in high-end smartphones to accelerate machine learning (A.I.) tasks. These include voice recognition and camera processing.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_44":{"id":"6df80d920455_44","__typename":"Paragraph","name":"ce8d","text":"Video encoder\u002Fdecoder — handles the power-efficient conversion of video files and formats.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_45":{"id":"6df80d920455_45","__typename":"Paragraph","name":"d9a8","text":"Secure Enclave — encryption, authentication, and security.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_46":{"id":"6df80d920455_46","__typename":"Paragraph","name":"2d2b","text":"Unified memory — allows the CPU, GPU, and other cores to quickly exchange information.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_47":{"id":"6df80d920455_47","__typename":"Paragraph","name":"967a","text":"This is part of the reason why a lot of people working on images and video editing with the M1 Macs are seeing such speed improvements. A lot of the tasks they do can run directly on specialized hardware. That is what allows a cheap M1 Mac Mini to encode a large video file without breaking a sweat while an expensive iMac has all its fans going full blast and still cannot keep up.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_48":{"id":"6df80d920455_48","__typename":"Paragraph","name":"39d6","text":"Read more about heterogeneous computing: Apple M1 foreshadows Rise of RISC-V.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":41,"end":76,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fapple-m1-foreshadows-risc-v-dd63a62b2562","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_49":{"id":"6df80d920455_49","__typename":"Paragraph","name":"4049","text":"In blue you see multiple CPU cores accessing memory, and in green you see large numbers of GPU cores accessing memory.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*SpFJ9g-taH9a-TvXdnaq2w.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":3,"end":7,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":60,"end":65,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_50":{"id":"6df80d920455_50","__typename":"Paragraph","name":"d906","text":"What is Special About Apple’s Unified Memory Architecture?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_51":{"id":"6df80d920455_51","__typename":"Paragraph","name":"956a","text":"Apple’s “Unified Memory Architecture” (UMA) is a bit tricky to wrap your head around (I got it wrong first time I wrote it down here).","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_52":{"id":"6df80d920455_52","__typename":"Paragraph","name":"8cb3","text":"To explain why, we need to take a few steps back.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_53":{"id":"6df80d920455_53","__typename":"Paragraph","name":"b7a7","text":"For a long time cheap computer systems have had the CPU and GPU integrated into the same chip (same silicon die). These have been famously slow. In the past saying “integrated graphics” was essentially the same as saying “slow graphics.”","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_54":{"id":"6df80d920455_54","__typename":"Paragraph","name":"a598","text":"These where slow for severals reasons:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_55":{"id":"6df80d920455_55","__typename":"Paragraph","name":"1d41","text":"Separate areas of this memory got reserved for the CPU and GPU. If the CPU had a chunk of data it wanted the GPU to use, it couldn’t say “here have some of my memory.” No, the CPU had to explicitly copy the whole chunk of data over the memory area controlled by the GPU.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_56":{"id":"6df80d920455_56","__typename":"Paragraph","name":"dd18","text":"CPUs don’t need a lot of data served, but they want it fast.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*7c67HhuDWVFM3Pi-mO5boA.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":55,"end":59,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_57":{"id":"6df80d920455_57","__typename":"Paragraph","name":"f669","text":"CPUs and GPUs don’t want their memory served the same way. Let us do a silly food analogy: CPUs want their plate of data served very quickly by the waiter, but they are totally cool with small portion sizes. Imagine a fancy French restaurant with waiters on rollerblades to serve you really quickly.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_58":{"id":"6df80d920455_58","__typename":"Paragraph","name":"cc63","text":"This is how your GPU wants their memory: huge portions. The more the merrier.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*ethYaJsPETw2zxF7Xm0Z0w.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":41,"end":45,"type":"STRONG","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_59":{"id":"6df80d920455_59","__typename":"Paragraph","name":"9c14","text":"GPUs in contrast are cool with the waiter being slow to serve the data. But the GPUs want enormous servings. They gobble massive amounts of data because they are massive parallel machines, that can chew through lots of data in parallel. Imagine an American junk food place, where the food takes some time to arrive because they are pushing a whole trolley of food to your seating area.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_60":{"id":"6df80d920455_60","__typename":"Paragraph","name":"812f","text":"With such different needs, putting CPUs and GPUs on the same physical chip was not a great idea. The GPUs would sit there starving while given small French servings. The result was that there was no point in putting powerful GPUs on an SoC. The tiny portions of data served up, could easily be chewed up by a weak little GPU.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_61":{"id":"6df80d920455_61","__typename":"Paragraph","name":"d539","text":"The second problem was that large GPUs produce a lot of heat and thus you cannot integrate them with the CPU without getting problems ridding yourself of the heat produced. Thus discrete graphics cards tend to look like the one below: Large beasts with massive cooling fans. They have special dedicated memory designed to serve the greedy cards massive amounts of data.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_62":{"id":"6df80d920455_62","__typename":"Paragraph","name":"303f","text":"GeForce RTX 3080","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*gQcbAlaUXNtjJi6OAUzMsg.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_63":{"id":"6df80d920455_63","__typename":"Paragraph","name":"14fa","text":"That is why these cards have high performance. But they have an achilles heel: Whenever they have to get data from the memory used by the CPU, this happens over a set of copper traces on the computer motherboard called a PCIe bus. Try chugging water through a super thin straw. It may get to your mouth fast, but the throughput is totally inadequate.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_64":{"id":"6df80d920455_64","__typename":"Paragraph","name":"5fca","text":"Apple’s Unified Memory Architecture tries to solve all these problems without having the disadvantages of old school shared memory. They achieve this in the following ways:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":8,"end":35,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_65":{"id":"6df80d920455_65","__typename":"Paragraph","name":"dade","text":"There is no special area reserved just for the CPU or just the GPU. Memory is allocated to both processors. They can both use the same memory. No copying is needed.","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_66":{"id":"6df80d920455_66","__typename":"Paragraph","name":"4c61","text":"Apple uses memory which serves both large chunks of data and serves it fast. In computer speak that is called low latency and high throughput. Thus the need to be connected to separate types of memory is removed.","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_67":{"id":"6df80d920455_67","__typename":"Paragraph","name":"2508","text":"Apple has gotten the watt usage of the GPU down, so that a relatively powerful GPU can be integrated without overheating the SoC. And ARM chips produce less heat, allowing the GPU to have a higher heat budget than a GPU on the same silicon die as an AMD or Intel CPU.","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_68":{"id":"6df80d920455_68","__typename":"Paragraph","name":"ba08","text":"Some will say unified memory is not entirely new. It is true that different systems have had it in the past. But then the difference in memory requirements may not have been as large. Secondly what Nvidia calls Unified Memory is not really the same thing. In the Nvidea world Unified Memory simply means that there is software and hardware which takes care of automatically copying data back and forth between the separate CPU and GPU memory. Thus from a programmers perspective Apple and Nvidia Unified Memory may look the same, but it is not the same in a physical sense.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_69":{"id":"6df80d920455_69","__typename":"Paragraph","name":"2fcb","text":"There is of course a tradeoff in this strategy. Getting this high bandwidth memory (big servings) require full integration which means you take away the opportunity from customers to upgrade their memory. But Apple seeks to minimize this problem by making the communication with the SSD disks so fast, that they essentially work like old fashion memory.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_70":{"id":"6df80d920455_70","__typename":"Paragraph","name":"ec91","text":"How Mac’s used GPUs before unified memory. There was even an option of having graphics cards outside the computer using a Thunderbolt 3 cable. There is some speculation that this may still be possible in the future.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*IJFHpc1CrblUt09PSzaTyg.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_71":{"id":"6df80d920455_71","__typename":"Paragraph","name":"d329","text":"If SoCs Are So Smart, Why Don’t Intel and AMD Copy This Strategy?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_72":{"id":"6df80d920455_72","__typename":"Paragraph","name":"f5e0","text":"If what Apple is doing is so smart, why is not everybody doing it? To some extent they are. Other ARM chip makers are increasingly putting in specialized hardware.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_73":{"id":"6df80d920455_73","__typename":"Paragraph","name":"2bdd","text":"AMD has also started putting stronger GPUs on some of their chips and moving gradually toward some form of SoC with the accelerated processing units (APU) which are basically CPU cores and GPU cores placed on the same silicon die.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_74":{"id":"6df80d920455_74","__typename":"Paragraph","name":"0602","text":"AMD Ryzen Accelerated Processing Unit (APU) which combines CPU and GPU (Radeon Vega) on one silicon chip. Does however not contain other co-processors, IO-controllers, or unified memory.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*vutPH0zsrwSzGgFWomL61A.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_75":{"id":"6df80d920455_75","__typename":"Paragraph","name":"279e","text":"Yet there are important reasons why they cannot do this. An SoC is essentially a whole computer on a chip. That makes it a more natural fit for an actual computer-maker, such as HP and Dell. Let me clarify with a silly car analogy: If your business model is to build and sell car engines, it would be an unusual leap to begin manufacturing and selling whole cars.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_76":{"id":"6df80d920455_76","__typename":"Paragraph","name":"04e1","text":"For ARM, in contrast, this isn’t an issue. Computer makers such as Dell or HP could simply license ARM intellectual property and buy IP for other chips, to add whatever specialized hardware they think their SoC should have. Next, they ship the finished design over to a semiconductor foundry such as GlobalFoundries or TSMC, which manufactures chips for AMD and Apple today.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":300,"end":315,"type":"A","href":"https:\u002F\u002Fen.wikipedia.org\u002Fwiki\u002FGlobalFoundries","anchorType":"LINK","userId":null,"linkMetadata":null},{"__typename":"Markup","start":319,"end":323,"type":"A","href":"https:\u002F\u002Fwww.tsmc.com\u002Fenglish","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_77":{"id":"6df80d920455_77","__typename":"Paragraph","name":"2ca8","text":"TSMC semiconductor foundry in Taiwan. TSMC manufactures chips for other companies such as AMD, Apple, Nvidia, and Qualcomm.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*d88lw8YMonKgdDWQLC1jXQ.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_78":{"id":"6df80d920455_78","__typename":"Paragraph","name":"a601","text":"Here we get a big problem with the Intel and AMD business model. Their business models are based on selling general-purpose CPUs, which people just slot onto a large PC motherboard. Thus computer-makers can simply buy motherboards, memory, CPUs, and graphics cards from different vendors and integrate them into one solution.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_79":{"id":"6df80d920455_79","__typename":"Paragraph","name":"7f77","text":"But we are quickly moving away from that world. In the new SoC world, you don’t assemble physical components from different vendors. Instead, you assemble IP (intellectual property) from different vendors. You buy the design for graphics cards, CPUs, modems, IO controllers, and other things from different vendors and use that to design an SoC in-house. Then you get a foundry to manufacture this.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_80":{"id":"6df80d920455_80","__typename":"Paragraph","name":"2fba","text":"Now you got a big problem, because neither Intel, AMD, or Nvidia are going to license their intellectual property to Dell or HP for them to make an SoC for their machines.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_81":{"id":"6df80d920455_81","__typename":"Paragraph","name":"b24c","text":"Sure Intel and AMD may simply begin to sell whole finished SoCs. But what are these to contain? PC-makers may have different ideas of what they should contain. You potentially get a conflict between Intel, AMD, Microsoft, and PC-makers about what sort of specialized chips should be included because these will need software support.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_82":{"id":"6df80d920455_82","__typename":"Paragraph","name":"558d","text":"For Apple this is simple. They control the whole widget. They give you, for example, the Core ML library for developers to write machine learning stuff. Whether Core ML runs on Apple’s CPU or the Neural Engine is an implementation detail developers don’t have to care about.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":129,"end":145,"type":"A","href":"https:\u002F\u002Fdeveloper.apple.com\u002Fmachine-learning\u002F","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_83":{"id":"6df80d920455_83","__typename":"Paragraph","name":"711f","text":"The fundamental challenge of making any CPU run fast","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_84":{"id":"6df80d920455_84","__typename":"Paragraph","name":"f11c","text":"So heterogeneous computing is part of the reason but not the sole reason. The fast general-purpose CPU cores on the M1, called Firestorm, are genuinely fast. This is a major deviation from ARM CPU cores in the past which tended to be very weak compared to AMD and Intel cores.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_85":{"id":"6df80d920455_85","__typename":"Paragraph","name":"b74c","text":"Firestorm, in contrast, beats most Intel cores and almost beats the fastest AMD Ryzen cores. Conventional wisdom said that was not going to happen.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_86":{"id":"6df80d920455_86","__typename":"Paragraph","name":"ab49","text":"Before talking about what makes Firestorm fast it helps to understand what the core idea of making a fast CPU is really about.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_87":{"id":"6df80d920455_87","__typename":"Paragraph","name":"92fc","text":"In principle you accomplish in a combination of two strategies:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_88":{"id":"6df80d920455_88","__typename":"Paragraph","name":"68be","text":"Perform more instructions in a sequence faster.","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_89":{"id":"6df80d920455_89","__typename":"Paragraph","name":"5f98","text":"Perform lots of instructions in parallel.","type":"OLI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_90":{"id":"6df80d920455_90","__typename":"Paragraph","name":"bd92","text":"Back in the ’80s, it was easy. Just increase the clock frequency and the instructions would finish faster. Every clock cycle is when the computer does something. But this something can be quite little. Thus an instruction may require multiple clock cycles to finish because it is made up of several smaller tasks.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":171,"end":180,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_91":{"id":"6df80d920455_91","__typename":"Paragraph","name":"905f","text":"However, today increasing the clock frequency is next to impossible. That is the whole “End of Moore’s Law” that people have been harping on for over a decade now.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_92":{"id":"6df80d920455_92","__typename":"Paragraph","name":"2133","text":"Thus it is really about executing as many instructions as possible in parallel.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_93":{"id":"6df80d920455_93","__typename":"Paragraph","name":"1f1b","text":"Multi-core or Out-of-Order processors?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_94":{"id":"6df80d920455_94","__typename":"Paragraph","name":"9966","text":"There are two approaches to this.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_95":{"id":"6df80d920455_95","__typename":"Paragraph","name":"23a9","text":"Add more CPU cores. Each core works independent and in parallel.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_96":{"id":"6df80d920455_96","__typename":"Paragraph","name":"1299","text":"Make each CPU core execute multiple instructions in parallel.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_97":{"id":"6df80d920455_97","__typename":"Paragraph","name":"6553","text":"For a software developer, adding cores is like adding threads. Every CPU core is like a hardware thread.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":54,"end":61,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_98":{"id":"6df80d920455_98","__typename":"Paragraph","name":"5a7a","text":"If you don’t know what a thread is, then you can think of it as the process of carrying out a task. With two cores, a CPU can carry out two separate tasks concurrently: two threads. The tasks could be described as two separate programs stores in memory or it could actually be the same program performed twice. Each thread needs some bookkeeping, such as where in a sequence of program instructions the thread is currently at. Each thread may store temporary results which should be kept separate.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":355,"end":360,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_99":{"id":"6df80d920455_99","__typename":"Paragraph","name":"8059","text":"In principle, a processor can have just one core and run multiple threads. In this case, it simply halts one thread and stores current progress before switching to another. Later it switches back. This doesn’t bring much of a performance enhancement unless the thread has to frequently halt to:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_100":{"id":"6df80d920455_100","__typename":"Paragraph","name":"e4a8","text":"Wait for input from the user","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_101":{"id":"6df80d920455_101","__typename":"Paragraph","name":"468b","text":"Data from a slow network connection, etc.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_102":{"id":"6df80d920455_102","__typename":"Paragraph","name":"5f6f","text":"Let us call these software threads. Hardware threads mean you have actual physical CPU cores at your disposal to speed up things.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_103":{"id":"6df80d920455_103","__typename":"Paragraph","name":"bdd7","text":"","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*2mDUgCX9a49EldiCTbL6fA.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_104":{"id":"6df80d920455_104","__typename":"Paragraph","name":"3d7f","text":"The problem with threads is that software developers have to write so called multi-threaded code. That is often difficult. In the past, this was some of the hardest code to write. However making server software multi-threaded tends to be easy. It is simply a matter of handling each user request on a separate thread. Thus in this case having lots of cores, is an obvious advantage. Especially for cloud services.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":195,"end":211,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_105":{"id":"6df80d920455_105","__typename":"Paragraph","name":"5a0b","text":"The Ampere Altra Max ARM CPU with 128 cores designed for cloud computing, where a lot of hardware threads is a benefit.","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*X5ZTLTHUYBdw0t25TemHcQ.png"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_106":{"id":"6df80d920455_106","__typename":"Paragraph","name":"f30f","text":"That is the reason why you see ARM CPU-makers such as Ampere making CPUs such as the Altra Max which has a crazy 128 cores. This chip is specifically made for the cloud. You don’t need crazy single-core performance, because in the cloud it is all about having as many threads as possible per watt to handle as many concurrent users as possible.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":85,"end":94,"type":"A","href":"https:\u002F\u002Fwww.networkworld.com\u002Farticle\u002F3564514\u002Fampere-announces-128-core-arm-server-processor.html","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_107":{"id":"6df80d920455_107","__typename":"Paragraph","name":"e162","text":"Read more about ARM CPUs with many cores: Are Servers Next for Apple?","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":42,"end":69,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fare-servers-next-for-apple-7992213d72c9","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_108":{"id":"6df80d920455_108","__typename":"Paragraph","name":"6ead","text":"Apple, in contrast, is on the complete opposite end of the spectrum. They make single-user devices. Lots of threads is not an advantage. Their devices are used for gaming, video editing, development, etc. They want desktops with beautiful responsive graphics and animations.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_109":{"id":"6df80d920455_109","__typename":"Paragraph","name":"e3ca","text":"Desktop software is generally not made to utilize lots of cores. For example, computer games will likely benefit from eight cores, but something like 128 cores would be a total waste. Instead, you would want fewer but more powerful cores.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_110":{"id":"6df80d920455_110","__typename":"Paragraph","name":"8ac1","text":"How Out-of-Order Execution Works","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_111":{"id":"6df80d920455_111","__typename":"Paragraph","name":"4cc9","text":"To make a more powerful core we need it to execute more instructions in parallel. Out-of-Order execution (OoOE) is a way to execute more instructions in parallel but without exposing that capability as multiple threads.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":82,"end":104,"type":"A","href":"https:\u002F\u002Fen.wikipedia.org\u002Fwiki\u002FOut-of-order_execution","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_112":{"id":"6df80d920455_112","__typename":"Paragraph","name":"4f36","text":"For an alternative solution read: Very Long Instruction Word Microprocessors","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":34,"end":76,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fvery-long-instruction-word-microprocessors-17262def3037","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_113":{"id":"6df80d920455_113","__typename":"Paragraph","name":"db59","text":"Developers don’t have to code their software specifically to take advantage of OoOE. Seen from the developer’s perspective it just looks like each core runs faster. Please note it is not a direct alternative to hardware threads. You want to use both, depending on the particular problem you are solving.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_114":{"id":"6df80d920455_114","__typename":"Paragraph","name":"2402","text":"To understand how OoOE works, you need to understand some things about memory. Asking for data in one particular memory location is slow. But the CPU is capable of getting getting many bytes at the same time. Hence getting 1 specific byte in memory, takes no less time than getting 100 more bytes following that byte in memory.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_115":{"id":"6df80d920455_115","__typename":"Paragraph","name":"6a52","text":"Robot pickers in a Warehouse for Komplett.no, an online store in Norway","type":"IMG","href":null,"layout":"INSET_CENTER","metadata":{"__ref":"ImageMetadata:1*IbuGfelqOOtcyX8NwTh-tw.jpeg"},"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_116":{"id":"6df80d920455_116","__typename":"Paragraph","name":"170f","text":"Here is an analogy: Consider pickers in a warehouse. Could be the little red robots in the picture above. Moving to multiple locations spread all over takes time. But picking up items from slots adjacent to each other is quick. Computer memory is very similar. You can quickly fetch content of memory cells which are adjecent.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_117":{"id":"6df80d920455_117","__typename":"Paragraph","name":"4d52","text":"Data is sent across what we call a databus. You can think of it as a road or pipe between memory and different parts of the CPU where data gets pushed through. In reality, it is of course just some copper tracks conducting electricity. If the databus is wide enough you can get multiple bytes at the same time.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_118":{"id":"6df80d920455_118","__typename":"Paragraph","name":"2053","text":"Thus CPUs get a whole chunk of instructions at a time to execute. But they are written to be executed one after the other. Modern microprocessors do what we call Out-of-Order execution (OoOE).","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_119":{"id":"6df80d920455_119","__typename":"Paragraph","name":"de65","text":"That means they are able to analyze a buffer of instructions quickly and see which ones depend on which. Look at the simple example below:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_120":{"id":"6df80d920455_120","__typename":"Paragraph","name":"4de2","text":"01: mul r1, r2, r3 \u002F\u002F r1 ← r2 × r3\n02: add r4, r1, 5 \u002F\u002F r4 ← r1 + 5\n03: add r6, r2, 1 \u002F\u002F r6 ← r2 + 1","type":"PRE","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":0,"end":111,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_121":{"id":"6df80d920455_121","__typename":"Paragraph","name":"d5a8","text":"Multiplication tends to be a slow process. So say it takes multiple clock cycles to perform. The second instruction will simply have to wait because its calculation depends on knowing the result that gets put into the r1 register.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":218,"end":220,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_122":{"id":"6df80d920455_122","__typename":"Paragraph","name":"d3b8","text":"However, the third instruction at line 03 doesn’t depend on calculations from previous instructions. Hence an Out-of-Order processor can begin calculating this instruction in parallel.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":39,"end":41,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_123":{"id":"6df80d920455_123","__typename":"Paragraph","name":"deba","text":"However more realistically we are talking about hundreds of instructions. The CPU is able to figure out all the dependencies between these instructions.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_124":{"id":"6df80d920455_124","__typename":"Paragraph","name":"b30b","text":"It analyses the instructions by looking at the inputs to each instruction. Do the inputs depend on output from one or more other instructions? By input and output, we mean registers containing results from previous calculations.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_125":{"id":"6df80d920455_125","__typename":"Paragraph","name":"d5b1","text":"For example, the add r4, r1, 5 instruction depends on input from r1 which is produced by mul r1, r2, r3 . We can chain together these relationships into long elaborate graphs that the CPU can work through. The nodes are the instructions and the edges are the registers connecting them.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":17,"end":30,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":65,"end":67,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":89,"end":103,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_126":{"id":"6df80d920455_126","__typename":"Paragraph","name":"621d","text":"The CPU can analyze such a graph of nodes and determine which instructions it can perform in parallel and where it needs to wait for the results from multiple dependent calculations before carrying on.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_127":{"id":"6df80d920455_127","__typename":"Paragraph","name":"46ee","text":"Many instructions will finish early but we cannot make their results official. We cannot commit them; otherwise, we supply the result in the wrong order. To the rest of the world, it has to look as if the instructions were carried out in the same sequence as they were issued.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_128":{"id":"6df80d920455_128","__typename":"Paragraph","name":"8815","text":"Like a stack, the CPU will keep popping done instructions from the top, until hitting an instruction that is not done.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_129":{"id":"6df80d920455_129","__typename":"Paragraph","name":"0770","text":"Basically you got two forms of parallelism: One that the developer must deal with explicitly when writing code and one that is entirely transparent. Of course the latter relies on lots of transistors on the CPU dedicated to Out-of-Order Execution magic. This is not a viable solution for small CPUs with few transistors.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_130":{"id":"6df80d920455_130","__typename":"Paragraph","name":"01ee","text":"It is the superior Out-of-Order execution that is making the Firestorm cores on the M1 kick ass and take names. It is in fact much stronger than anything from Intel or AMD and they may never be able to catch up. To understand why, we need to get into some more technical details.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_131":{"id":"6df80d920455_131","__typename":"Paragraph","name":"52fe","text":"ISA Instructions vs Micro-Operations","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_132":{"id":"6df80d920455_132","__typename":"Paragraph","name":"c057","text":"Previously I skipped some details on how Out-of-Order Execution (OoOE) works.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_133":{"id":"6df80d920455_133","__typename":"Paragraph","name":"5a6b","text":"Programs loaded into memory are made up of machine code instructions designed for specific Instruction-Set Architectures (ISA) such as x86, ARM, PowerPC, 68K, MIPS, AVR etc.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_134":{"id":"6df80d920455_134","__typename":"Paragraph","name":"c8b7","text":"For instance the x86 instruction to fetch a number from memory location 24 into a register you may write:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_135":{"id":"6df80d920455_135","__typename":"Paragraph","name":"bc03","text":"MOV ax, 24","type":"PRE","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_136":{"id":"6df80d920455_136","__typename":"Paragraph","name":"c6bc","text":"x86 have registers named ax, bx, cx and dx(remember these are the memory cells inside the CPU you perform operations on). However the equivalent ARM instruction would look like this:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":25,"end":27,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":29,"end":31,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":33,"end":35,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":40,"end":42,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_137":{"id":"6df80d920455_137","__typename":"Paragraph","name":"64d0","text":"LDR r0, 24","type":"PRE","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_138":{"id":"6df80d920455_138","__typename":"Paragraph","name":"4cd1","text":"AMD and Intel processors understand the x86 ISA, while Apple Silicon chips, such as M1, understand the ARM Instruction-Set Architecture (ISA).","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_139":{"id":"6df80d920455_139","__typename":"Paragraph","name":"2266","text":"However internally the CPU works on an entirely different instruction-set invisible to the programmer. We call these micro-operations (micro-ops or μops). These are the instructions the Out-of-Order hardware works with.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_140":{"id":"6df80d920455_140","__typename":"Paragraph","name":"a998","text":"But why can’t the OoOE hardware work with regular machine code instructions? Because the CPU needs to attach lots of different information to the instructions to be able to run them in parallel.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_141":{"id":"6df80d920455_141","__typename":"Paragraph","name":"8d96","text":"Thus while a normal ARM instruction may be 32-bit (32 digits of 0 and 1), a micro-op can be much longer. It contains information about its order.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_142":{"id":"6df80d920455_142","__typename":"Paragraph","name":"a55d","text":"01: mul r1, r2, r3 \u002F\u002F r1 ← r2 × r3\n02: add r4, r1, 5 \u002F\u002F r4 ← r1 + 5\n03: add r1, r2, 1 \u002F\u002F r1 ← r2 + 1","type":"PRE","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":0,"end":111,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_143":{"id":"6df80d920455_143","__typename":"Paragraph","name":"0c5e","text":"Consider if we run instruction 01: mul and 03: add in parallel. Both store their result in register r1 . If we write the result of instruction 03: add before 01: mul, then instruction 02: add will get the wrong input. Hence it is very important to keep track of instruction order. The order is stored with each micro-op. It also stores e.g. that instruction 02: add depends on output from 01: mul.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":31,"end":38,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":43,"end":50,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":100,"end":102,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":143,"end":150,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":158,"end":165,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":184,"end":191,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":358,"end":365,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null},{"__typename":"Markup","start":389,"end":396,"type":"CODE","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_144":{"id":"6df80d920455_144","__typename":"Paragraph","name":"64b5","text":"That is why we cannot have programs written using micro-ops. They contain lots of details specific to the internals of each microprocessor. Two ARM processors could have very different micro-ops internally.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_145":{"id":"6df80d920455_145","__typename":"Paragraph","name":"31fb","text":"Read more about CPUs with micro-ops like instructions: Very Long Instruction Word Microprocessors.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":55,"end":98,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fvery-long-instruction-word-microprocessors-17262def3037","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_146":{"id":"6df80d920455_146","__typename":"Paragraph","name":"3180","text":"Also, micro-ops are usually easier to work with for the CPU. Why? Because they each do one simple limited task. Regular ISA instructions can be more complex causing a bunch of stuff to happen and thus frequently translate to multiple micro-ops. Thus the name “micro” comes from the small task they do, not the length of the instruction in memory.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":87,"end":90,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_147":{"id":"6df80d920455_147","__typename":"Paragraph","name":"ff1f","text":"For CISC CPUs there is usually no alternative but to use micro-ops otherwise the large complex CISC instructions would make pipelines and OoOE next to impossible to achieve.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_148":{"id":"6df80d920455_148","__typename":"Paragraph","name":"4d71","text":"Read more: Why Pipeline a Microprocessor?","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":11,"end":41,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fmicroprocessor-pipelining-f63df4ee60cf","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_149":{"id":"6df80d920455_149","__typename":"Paragraph","name":"9da7","text":"RISC CPUs have a choice. So, for example, smaller ARM CPUs don’t use micro-ops at all. But that also means they cannot do things such as OoOE.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_150":{"id":"6df80d920455_150","__typename":"Paragraph","name":"b27b","text":"Why is AMD and Intel Out-of-Order execution inferior to M1?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_151":{"id":"6df80d920455_151","__typename":"Paragraph","name":"cd20","text":"But you wonder, why does any of this matter? Why is this detail important to know to understand why Apple has the upper hand on AMD and Intel?","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_152":{"id":"6df80d920455_152","__typename":"Paragraph","name":"8286","text":"It is because the ability to run fast depends on how quickly you can fill up a buffer of micro-operations. If you got a large buffer then the OoOE hardware will have an easier time to locate two or more instructions which it can run in parallel. But there is no point in having a large instruction buffer if you cannot refill it fast enough after instructions get picked and executed.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_153":{"id":"6df80d920455_153","__typename":"Paragraph","name":"5cf7","text":"The ability to refill the instruction buffer quickly relies on the ability to quickly chop machine code instruction into micro-ops. The hardware units that does this are called decoders.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":177,"end":185,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_154":{"id":"6df80d920455_154","__typename":"Paragraph","name":"d0d8","text":"And finally we get to the killer feature of the M1. The biggest and meanest Intel and AMD microprocessor have a total of four decoders busy cutting machine code instructions into micro-ops.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_155":{"id":"6df80d920455_155","__typename":"Paragraph","name":"8622","text":"But this is no match for the M1, which has an absolutely unheard of number of decoders: Eight. Significantly more than anybody else in the industry. That means it can fill up the instruction buffer much quicker.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_156":{"id":"6df80d920455_156","__typename":"Paragraph","name":"0669","text":"To deal with this the M1 also has an instruction buffer which is 3x times larger than what is normal in the industry.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_157":{"id":"6df80d920455_157","__typename":"Paragraph","name":"59ff","text":"Why can’t Intel and AMD add more instruction decoders?","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_158":{"id":"6df80d920455_158","__typename":"Paragraph","name":"4735","text":"This is where we finally see the revenge of RISC, and where the fact that the M1 Firestorm core has an ARM RISC architecture begins to matter.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_159":{"id":"6df80d920455_159","__typename":"Paragraph","name":"fca4","text":"You see, an x86 instruction can be anywhere from 1–15 bytes long. RISC instructions have fixed length. Every ARM instruction is 4 bytes long. Why is that relevant in this case?","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_160":{"id":"6df80d920455_160","__typename":"Paragraph","name":"d102","text":"Because splitting up a stream of bytes into instructions to feed into eight different decoders in parallel becomes trivial if every instruction has the same length.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_161":{"id":"6df80d920455_161","__typename":"Paragraph","name":"b4e4","text":"However, on an x86 CPU, the decoders have no clue where the next instruction starts. It has to actually analyze each instruction in order to see how long it is.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":50,"end":55,"type":"EM","href":null,"anchorType":null,"userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_162":{"id":"6df80d920455_162","__typename":"Paragraph","name":"e842","text":"The brute force way Intel and AMD deal with this is by simply attempting to decode instructions at every possible starting point. That means x86 chips have to deal with lots of wrong guesses and mistakes which has to be discarded. This creates such a convoluted and complicated decoder stage that it is really hard to add more decoders. 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For instance if every x86 instruction turned into 2 micro-ops while every ARM instruction turned into 1 micro-op, then four x86 decoders would produce the same number of micro-ops per clock cycle as an ARM CPU with 8 decoders.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_166":{"id":"6df80d920455_166","__typename":"Paragraph","name":"b2f1","text":"Except this is not the case in the real world. Highly optimized x86 code rarely uses complex CISC instructions, which would translate into many micro-ops. In fact most will only translate into 1 micro-op.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_167":{"id":"6df80d920455_167","__typename":"Paragraph","name":"8792","text":"However all these simple x86 instructions don’t help Intel or AMD. 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The Zen3 is just barely squeezing past Firestorm despite having almost 60% higher clock frequency.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_170":{"id":"6df80d920455_170","__typename":"Paragraph","name":"da9f","text":"So why doesn’t Apple increase the clock frequency too? Because higher clock frequency makes the chips run hotter. That is one of Apple’s key selling points. Their computers — unlike Intel and AMD offerings — barely need cooling.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_171":{"id":"6df80d920455_171","__typename":"Paragraph","name":"f640","text":"In essence, one could say Firestorm cores really are superior to Zen3 cores. Zen3 only manages to stay in the game by drawing a lot more current and getting a lot hotter. Something Apple simply chooses not to do.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_172":{"id":"6df80d920455_172","__typename":"Paragraph","name":"6302","text":"If Apple wants higher performance they are simply going to add more cores. That lets them keep watt usage down while offering more performance.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_173":{"id":"6df80d920455_173","__typename":"Paragraph","name":"e95d","text":"The future","type":"H4","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_174":{"id":"6df80d920455_174","__typename":"Paragraph","name":"9450","text":"It seems AMD and Intel have painted themselves into a corner on two fronts:","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_175":{"id":"6df80d920455_175","__typename":"Paragraph","name":"9af9","text":"They don’t have a business model that makes it easy to pursue heterogeneous computing and SoC designs.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_176":{"id":"6df80d920455_176","__typename":"Paragraph","name":"7c75","text":"Their legacy x86 CISC instruction set is coming back to haunt them, making it hard to improve OoO performance.","type":"ULI","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_177":{"id":"6df80d920455_177","__typename":"Paragraph","name":"8380","text":"Read more: Intel, ARM and the Innovators Dilemma","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[{"__typename":"Markup","start":11,"end":48,"type":"A","href":"https:\u002F\u002Ferik-engheim.medium.com\u002Fintel-arm-and-the-innovators-dilemma-a9ebd20ea200","anchorType":"LINK","userId":null,"linkMetadata":null}],"dropCapImage":null},"Paragraph:6df80d920455_178":{"id":"6df80d920455_178","__typename":"Paragraph","name":"0ff6","text":"It doesn’t mean game over. They can increase the clock frequency and use more cooling, throw in more cores, beef up the CPU caches, etc. But they are both at a disadvantage. Intel is in the worst situation, as their cores are already soundly beaten by Firestorm, and they have weak GPUs to integrate with an SoC solution.","type":"P","href":null,"layout":null,"metadata":null,"hasDropCap":null,"iframe":null,"mixtapeMetadata":null,"markups":[],"dropCapImage":null},"Paragraph:6df80d920455_179":{"id":"6df80d920455_179","__typename":"Paragraph","name":"cd04","text":"The problem with throwing in more cores is that for typical desktop workloads you reach diminishing returns with too many cores. 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